JPH03250970A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device for digitally performing special processing such as pattern images on characters.

(Prior Art) Conventionally, an image processing device such as a copying machine processes an original image by 1:
1, or processing such as reduction/enlargement, but with the adoption of digital processing technology, processing such as decoration is being considered. This processing includes, for example, processing such as edging and shadowing.

Along with such processing, the coloring process has also become an important theme. Conventionally, black-and-white digital copying machines and the like basically use a combination of black and white, so sub-images created by image processing are colored with gray, which is an intermediate tone.

However, since there are about three color components for a color image, it is difficult to determine which color to color the image with.

A method has already been proposed that uses seven colors close to the original colors. When expressed with colors close to the original in this way, the emphasis may be weak, so in order to make the emphasis stronger relative to the original, we created an inverted color of seven colors close to the original (
It is expressed using complementary colors.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, only the emphasis processing is performed using an inverted color, and there is no flexibility in processing contents.

Furthermore, since the background color is always white, it is not possible to perform corresponding processing even though there are actually many background colors other than white.

The present invention has been made in view of the above, and a first object thereof is to perform free emphasis processing using a plurality of colors.

A second purpose is to perform sub-image processing using a background color other than white.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a binarization processing means for binarizing input image data for each of R, G, and B, and a binarization processing means for binarizing input image data for each of R, G, and B. An image provided with a storage means for storing, an image processing means for forming a sub-image based on data read from the storage means, and a coloring processing means for coloring the sub-image by the image processing means with an inverted color. A processing device is provided.

In addition, in order to perform sub-image processing on background colors other than white, input image data is
an image processing means for forming a sub-image based on the data read from the storage means; The present invention provides an image processing device including a coloring processing means for coloring.

[Effect]

According to the image processing device of the present invention, a sub-image is formed for binary data depending on whether or not the basic image is white, and designated colors corresponding to a plurality of modes are selected for the sub-image,
As a result, coloring with an inverted color is performed. Therefore, emphasis processing using a plurality of colors becomes possible.

In addition, the specified background color is binarized according to the threshold value, and a sub-image is formed for the R, G, B data.
This is added to each input image and mixed to perform coloring processing. Therefore, it becomes possible to perform sub-image processing even if the background color is a color other than white.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to the present invention, and FIG. 2 is a block diagram showing details of the image processing section 102 in FIG. 1.

In FIG. 1, the image processing device includes an image reading section 101 that optically reads an image of a document or the like and outputs it as an electrical signal, an image processing section 102 that digitally processes the signal from the image reading section 101, and an image processing section 102 that digitally processes the signal from the image reading section 101. An image recording unit 10 that hard copies the signal obtained by the processing unit 102 or stores it in a recording medium such as a magnetic disk.
Consists of 3.

As shown in FIG.
Binarization processing units 201a, 201b, and 201 that binarize each of the three primary colors, zreen) and B (Blue).
c. Line memory sections 202a, 202b, 202C1 which store 9947 portions of the processing results of the binarization processing sections 201a, 201b, 201c.
1) Coloring is performed based on the image processing unit 203 that forms a sub-image on the basic image data for a line, and the output data of the image processing unit 203 and R, G, B color information. 204a, 204b, and 204C.

FIG. 3 is a circuit diagram showing details of the configuration of one of the binarization processing units 201a, 201b, and 201C.

The binarization processing section 201 includes a comparator 301 and a threshold register 302. Threshold register 30
In 2, a threshold value for disulfidation is set in advance from the CPU. If the input image data is at a level exceeding the threshold, the comparator 301 generates an "L II level signal (DATA) at the output terminal. The relationship between the input image data and DATA in this case is as shown in the table below. It is.

In the above table, the °′H′” level of the input image data is
The input data exceeds the threshold and is "L".

The level indicates input data other than the threshold value.

Figure 4 shows line memory sections 202a, 202b, 202C.
1 shows a detailed configuration of one.

The line memory section 202 includes registers 40L, ~401
1 and a memory section 402.

Each of the registers 401-, 401-, and l includes an input terminal D, an output terminal Q, and a clock terminal CL (negative logic), and the input terminals are commonly connected and data is applied thereto. Further, a clock terminal CL is also commonly connected, and a synchronization signal is applied to this terminal.

Also, registers 401-I to 401-1. Each of the
A clock signal CLK is applied.

The memory section 402 has data input terminals D0□, ~Dlnl
+in, data output terminal D0°, ~D In-Ho.

71, read clock terminal RD CL K, write clock terminal WRCL K, write enable input terminal WE, read enable input terminal RE, reset write input terminal R3TW, and reset read input terminal R5T
It is a one-chip IC equipped with R.

Note that CLK is a data clock signal and LSYNC is a line synchronization signal.

In the configuration shown in FIG. 4, 1-bit data input is delayed by 1 clock in registers 401-t to 401-, and data output D0°□ is input to registers 401-+ to 401-I. , the input data D1.7 is delayed by one clock. By repeating similar processing until the input data D (,, -11 inches), the output of the line memory section 402 is
With a shift of 5 degrees, it is possible to extract n942 worth of data. Then, the data output terminals D0°, ~D (r+-1
Adds n-bit data of 1°□ and 1-bit input data, and outputs (n+1) bits of data (OUT
The data shown in FIG. 4 is sent out as PUT).

In Figure 5, the shaded area indicates input 1-bit data, the dotted line frame with number 1 indicates data shifted by one line, the dotted line frame with number 2 indicates data shifted by two lines, and the dotted line frame with number 3 indicates data shifted by three lines. are shown respectively.

FIG. 6 is a circuit diagram showing details of the image processing section 203.

Output 0 of line memory units 202a, 202b, 202c
Each of UTPtJT R, G, and B includes an n input to output 1 selector 6 having n input terminals D0 to D7-1.
01a, 601b, and 601c are connected to each other, and the output of the shadow width register 602 is applied to the select terminal S thereof.

In addition, for the outputs R, G, and B, a three-man powered OR gate 603 is used.
, and an inverter 604 is connected to the output terminal of this OR gate 603. Furthermore, selectors 601a and 60lb.

Each output terminal Y of 601C has a three-man OR gate 60.
5 is connected, and an AND gate 606 is provided to perform a logical product of this output and the output of an inverter 604. Further, an inverter 607 is connected to invert the output signal of the selector 601a, and color information R is output from the inverter 607.

Similarly, an inverter 608 is connected to the output terminal Y of the selector 601b, and its inverted output is output as color information G. In addition, the output terminal Y of the selector 601c has
Inverter 609 is connected, and its inverted output is color information B.
is output as

In the configuration of FIG. 6, the binarized outputs R, G,
B (data 0) is applied as is to the OR game) 603. On the other hand, line memory sections 202a, 202b, 2
Outputs 1 to (n-1) of 02C are selected from selectors 601a and 601a.
01b.

601C, and the outputs of these selectors are set according to the preset value of the shadow width register 602.
One arbitrary line is selected. For example, when n is 3,
Either of the dotted line frame data 1.2.3 shown in FIG. 5 is selected.

Each of the outputs of selectors 601a, 601b, and 601C is inverted by each of inverters 607, 608, and 609, and output as color information R, G, and B, respectively. These inverters are provided to restore data inverted during binarization to its original state.

Further, the OR gate 603 is provided to determine whether the basic image is white or other than white.
605 is provided to determine whether the sub-image is white or other than white. Each process in this case is as shown in the table below (H and L in the table indicate output levels).

FIG. 7 is a circuit diagram showing details of the processing section 204 in color.

The CPU (not shown) has a specified color register 70 on its bus.
1. Off-level register 702 and mode switching register 703 are connected in parallel, and input terminal A of selector 704 is connected to designated color register 701 and off-level register 702.
, B are connected.

Furthermore, one input terminal of a two-manual AND gate 705 is connected to the mode switching register 703, and color information X is input to the other input terminal.

Furthermore, the output signal of the AND gate 705 is transmitted to the selector 70
It is applied to the select terminal S of No. 4.

The input terminal B of the selector 706 is connected to the output terminal Y of the selector 704, the input image data X is applied to the input terminal A, and the processing result (
AND gate 606 output of FIG. 6) is applied. Output image data X is output from the output terminal Y of the selector 706.

Next, regarding the operation of the configuration shown in Fig. 7, we will explain ■ specified color mode,
■Standard 7-color mode, ■Reverse color (complementary color) 7-color mode will be explained in this order.

(2) Specified color mode The mode switching register 703 is set to single color mode, and its output is set to the "L" level. As a result, the output of the AND gate 705 is always at the "L" level, and the specified color register 19 is selected.

Next, the output of the selector 706 is selected by the processed signal, and when the processed signal is off (non-sub-image part), input image data X is selected, and when it is on (sub-image part), the selector 704 is selected. selected, rate setting color register 701
The output data (specified color) is output.

Through these operations, as shown in FIG.
), a shaded image like (d) can be obtained.

■ Standard 7-color mode The mode switching register 703 is selected so that the output becomes “H1 level.” As a result, the AND gate 705
The input data of color information is output as is.

When the color information is on (H1 level), the selector 704 selects the value of the off level register 702 and turns it off (“
L'' level), the value of the designated color register 701 is selected.

The selector 706 performs the same operation as in the specified color mode described above.

Here, set the maximum concentration to "1" in the off level register 702.
"1" is input as "1", and "°0.5" is input as intermediate density ro and 5J in designated color register 701. Thereby, the sub-image can be given a color that is an intermediate tone compared to the hue of the original data. The combination of color information and sub-image data allows the following color settings.

By the process shown in 2, it is possible to obtain an output image as shown in FIG. 8(b) for the document (a) shown in FIG.

(2) Inverted color (complementary color) 7-color mode This mode is the same as the standard 7-color mode except for the setting of the off-level register 702. In this case, "0" is input to the off-level register 702 with the lowest density set to "0".Thereby, the sub-image can be colored in a complementary color to the original data.

In this mode, the following color settings can be made by combining color information and sub-image data.

Through this process, (C
) you can get an output image like this.

Note that instead of the line memory section having the configuration shown in FIG. 4, the configuration shown in FIG. 9 may be used. This configuration consists of register 4
The feature is that 01-+ to 401□ are removed and data R, data G, and data B can be input.

In this configuration, 1-bit input data is used as data input. ,
n, data output D0°, input data D l i
I set it to n. This kind of treatment is applied to the input data D In-
By repeating this process up to 11 inches, it becomes possible to have 0942 line memory outputs. And then, Do. □
〜D〉. , n-bit data (in this example, n-2
) and the input 1-bit data, and outputs (n+1) bits of data.

FIG. 10 is a circuit diagram showing another example of the image processing section 203.

The image processing section 203 includes a storage section 1001 and an edging circuit 1002. Pixels in the pixel direction (main scanning direction) are arranged by each register of the storage unit 1001, and then thinning processing and thickening processing in the pixel direction are performed by the edging circuit 1002 as shown in FIG.

In the circuit shown in FIG. 10, the data that enters the edging circuit 1002 after one register is indicative of the position of the center pixel. Further, the edging circuit 1002 has a logic configuration in which adjacent pixels do not interfere with each other, and color information R, G, and B are outputted via inverters 607 to 609, similar to the configuration shown in FIG.

When this circuit is used, the processing by the coloring processing unit 204 in each mode is as follows.

■ Specified color mode An image in which R, G, and B are all the same color as shown in (e) in Figure 8.

■ Standard 7 color mode Image of FIG. 8(e).

■ Inverted color (complementary color) 7 color mode Image of FIG. 8(d).

In the above, the border characters and shading have been described for characters, but the present invention is not limited to this, and the present invention can be applied to processing for coloring all sub-images. In addition, a specified color register 701 and an off-level register 70
The setting value of 2 can be set to any value.

Next, background processing will be explained.

In this process, 2 (li conversion processing units 201a, 20
Specify any one of the eight background colors (red, green, blue, cyan, magenta, yellow-white, black) using 1b and 201c, and perform binarization based on a separately set threshold. .

The obtained color data is stored for (n+1) lines in the inner memory sections 202a, 202b, and 202c for each of R, G, and B, respectively. The image processing unit 203 performs a process of adding a sub-image to a basic image corresponding to a color original.

On the other hand, the coloring processing units 204a to 204c process the image processing unit 203 according to specified conditions for each input image.
Override the subimage created in . At this time, a standard seven-color mode is executed based on the color information, which is an additive mixture of the background color and the basic image. Additionally, inverted colors (complementary colors)
Processing using seven color modes is also possible. It is also possible to perform processing using a designated color mode that does not refer to color information.

FIG. 12 is a circuit diagram showing the configuration of a binarization processing section for background processing.

The binarization processing section shown here includes a threshold register 120, a comparator 1202, and an exclusive OR gate (Exclusive OR) 1203. A threshold value is set in the threshold register 1201 by the CPU in advance during binarization.

Exclusive OR gate 1203 outputs an "L" level signal when the image data is at a level below the threshold value. This becomes standard mode. Moreover, when the threshold value is exceeded, an "H" level signal is outputted, and the mode becomes inversion mode.

The relationship between the threshold value and color for the background color is as shown in the table below.

The circuit of the coloring processing unit 204 in the second background color processing is the seventh one.
As shown in the figure, the shading is processed as shown in FIG. Further, in each mode, an image is formed as follows.

■ Specified color mode The image shown in FIG. 13(d) is obtained.

■ Standard 7-color mode In this case, the maximum density or minimum density is set in the off-level register 702. In the settings, when binarizing,
In the standard mode, the threshold value is set to "1" with the highest density set to "1", and in the reverse mode, the threshold value is set to "0" with the lowest density set to "1".
and set it to '0'°.

The resulting color is as shown in FIG. 14, which is an additive mixture of the basic image and background color.

In response to the original image input in (a) of Figure 13, the colors of ■゛, ■゛■゛, which are an additive mixture of the background color and the basic image, are shown in (b).
It is attached like this.

(2) Inverted color (complementary color) mode This is achieved by setting the off-level register 702 to a value opposite to that in the standard 7-color mode. At this time, the designated color register 701 is set to 0.5, which indicates the intermediate tone. The color obtained here is as shown in FIG. 14, and is the value obtained by additively mixing the basic image and the background color and inverting this.

In this case, in contrast to (a) in Figure 13, the background color and the basic image are additively mixed and this is inverted, ■°°, ■゛°
,■“ is colored as shown in (e).

In the above, shading has been explained for characters, but the present invention is not limited to this, and it is possible to perform coloring for all sub-images. Furthermore, the values of the off-level register 702 and designated color register 701 are as follows:
It is possible to set it arbitrarily.

Also, when coloring, to adjust the color balance,
The coloring processing section 204 can be configured as shown in FIG. The basic configuration of this circuit is based on FIG.

In other words, the specified color register and off-level register are set to R.
, G, B, designated color registers 701a, 701b, 7
01c and off-level registers 702a, 702b, 7
02c is provided, a selector 704a is connected to each output of the designated color register 701a and the off-level register 702a, and a selector 704a is connected to each output of the designated color register 701b and the off-level register 70.
A selector 704b is connected to each output of the register 2b, and a selector 704C is connected to each output of the designated color register 01c and off-level register 702C.

Also, this off-level register 702a.

AND gate 1501a to apply a select signal to each select terminal S of 702b, 702c.

1501b and 1501c are provided, and color information and data from the CPU bus are applied to each input. Each output of selectors 704a, 704b, and 704C is applied to table memory 1502, and each of selectors 706a, 706b, and 706C is connected to the three outputs.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

The image processing apparatus according to claim 1 includes a binarization processing means for binarizing input image data for each of R, G, and B, and storing data for a plurality of lines for each of R, G, and B. Since the configuration includes a storage means, an image processing means for forming a sub-image based on data read from the storage means, and a coloring processing means for coloring the sub-image by the image processing means with an inverted color, Emphasis processing using multiple colors becomes possible.

Further, in the image processing apparatus according to claim 2, the input image data is binarized according to a designated background color, and means for storing the binarized data for each of R, G, and B, and based on the data read from the storage means, Since the image processing means for forming a sub-image and the coloring processing means for coloring the sub-image by the image processing means with reference to the background color are provided, even if the background color is a color other than the white standard, the sub-image can be colored. It becomes possible to perform image processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing device according to the present invention, FIG. 2 is a block diagram showing details of the image processing section 2 in FIG. 1, and FIG. 3 is a configuration of one of the binarization processing sections. 4 is a circuit diagram showing the detailed configuration of one of the line memory sections, FIG. 5 is an explanatory diagram showing the select I/processing of the present invention, and FIG. 6 is a circuit diagram showing details of the image processing section. 7 is a colored circuit diagram showing the details of the processing section, FIG. 8 is an explanatory diagram showing the processing of the present invention with shading, and FIG. 9 is a circuit showing another example of the line memory section. Figure 10 is a circuit diagram showing another example of the image processing section, Figure 11 is an explanatory diagram showing thinning processing and thickening processing by the edging circuit in Figure 10, and Figure 12 is for background processing. Circuit diagram showing the configuration of the binarization processing unit of
Figure 3 is an explanatory diagram showing the shading in background color processing,
Fig. 14 is a color scheme diagram showing the color combination when the basic image and background color are mixed additively, and Fig. 15 is a circuit diagram showing the configuration of the coloring processing section for adjusting the color balance when coloring is performed. be. Explanation of symbols 101 - Image reading section 102 - Image processing section 103 -
・Image recording unit 201a ~ 201c-binarization processing unit 202a ~
202cm Line memory section 203-Image processing section 204a to 207c-・Coloring is done by processing section 301=・
- Comparator 302... - Threshold register 601a ~ 601c, 704.704a ~ 704c
706 706a ~ Ma06cm selector 602 -- Shadow width register low 03 605 -- OR gate 606, 705.1501a ~ 1501C -- AND gate 607.608, 609 -- Inverter 701 7
01a ~701cm Specified color register 702 702a
~702cm Off level off level register Off level register 03 conversion register 1002-Edging circuit 1502--Table memory

Claims (2)

[Claims] (1) Binarize input image data for each R, G, and B2
digitization processing means; storage means for storing a plurality of lines of data for each of R, G, and B; image processing means for forming a sub-image based on the data read from the storage means; An image processing apparatus comprising: a coloring processing means for coloring a sub-image produced by the processing means with an inverted color. (2) means for binarizing input image data according to a designated background color and storing it for each of R, G, and B; and image processing means for forming a sub-image based on the data read from the storage means; An image processing device comprising: coloring processing means for coloring the sub-image produced by the image processing means with reference to a background color.