JPH03250975A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION C. Industrial Application Field 1 The present invention relates to an image processing device, and particularly to processing for restoring a multivalued image from a binary image.

[Conventional technology] Conventionally, as a technology for restoring a binary image to a multivalued image,
Multivalue conversion is performed using a smoothing filter. Also,
A method has also been proposed in which the smoothing filter is switched in response to the bang of the binary image.

[Problem to be solved by the invention] However, in the past, for simple slam recognition,
There was a drawback that switching malfunctions occurred.

Furthermore, when the binary image has a periodic structure such as a dither image, there is a drawback that the bang detection becomes difficult and proper filter switching cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that can appropriately restore a multivalued image from a binary image.

[Means for Solving the Problems] The present invention includes an image processing means, an output means for outputting a plurality of differential signals with respect to an image signal to be processed, a selection means for selecting a differential signal, and a method based on the selected differential signal. and a control means for controlling the image processing means.

[Operation] In the present invention, by selecting a differential filter that is not affected by the periodic structure of the image to be processed, multi-value conversion can be performed without being affected by the frequency of the image to be processed.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of an image processing circuit according to the present invention.

In this circuit, a binary input image signal is transferred to a latch 2-1 consisting of a 5-line buffer section and a D flip-flop.
is input.

The 5-line buffer section l is composed of FIFO etc.
The image for 5 vertical lines is buffered, and data at the same horizontal position is sequentially output to latch 2-7.2-
13.2-19.2-25.2-31.

These latched image data are further latched and finally latched 2-6.2-12.2-18
．． 2-24.2-30.2-36, and as a result, data in a continuous rectangular area of 6 pixels x 6 pixels is latched in latches 2-1 to 2-36.

The latch output QO-Q35 is transmitted through the first filtering section 3, the second filtering s4, and the first filtering section 5.
, the fourth filter 7, and the fifth filter 8.

In the first filtering section 3, FIG. 2 (A-1) and (
The square root of the sum of squares of each filter in B-1) or the sum of absolute values of each filter is calculated.

Similarly, in the second filtering section 4, as shown in FIG.
and (B-2) are performed. Furthermore, in the same way, the third filtering section 5 also performs
-3) The square root of the sum of squares or the sum of absolute values of each filter is calculated.

Figure 2 (A-1) to (A-3) and (B-1) to (B
-3) filtering has a configuration as shown in FIG.
The integrator 42 calculates the sum of pixels corresponding to the negative element, and the subtracter 43 subtracts the sum.

Furthermore, the filtering of FIG. 2(A-1) can be achieved using the circuit of FIG. 3(B), and the filtering of FIG. 2(A-2) and (A-3) is also possible using a similar circuit. . That is, four pixels in the vertical direction at the same horizontal position are input to the adder 44 and the sum is output.
5, and after a delay of one pixel, the adder 46 adds the pixel before the delay and outputs the sum of 2 horizontal pixels x 4 vertical pixels.

Next, a delay of t=4 is performed in the t pixel delay unit 47,
The subtraction unit 48 performs subtraction to finally obtain the output shown in FIG. 2 (A-1).

The respective outputs of the first filtering section 3, the second filtering section 4, and the third filtering section 5 having the above configuration example are input to the selector 6, and one of the outputs is set to PTS.
Selected according to the EL signal. PTSEL signal is input 2
A CPU (not shown) or the like compares the period T of the value image and the period t of the first to third filtering sections, and selects the signal of the filtering section in which T and t are the closest or match. The zero period t to be controlled is shown in FIG. 2 (A-1),
(B-1), (A-2), (B-2), (A-3), (
As shown in B-3), it is the center distance of the positive and negative kernel elements of each differential filter.

In addition, as shown in FIG. 4, inside the fourth filter 7,
Three filters with S=4.3.2 are built in,
Of the three filters, the filter with S=t is selected and output by the PTSEL signal so that S=t.

With the above operation, if the input binary image is a dither image with a one-pixel period, the first-order differential filter (Fig. 2 (A-T), (B-T)) that is less affected by the periodic structure or a smoothing filter (FIG. 4, CD-T with S=j)) is selected.

In this way, the fourth filter 7 restores the binary image to a multivalued image using the smoothing filter, but similarly, the fifth filter 8 restores the pixel of interest to a large value, as shown in FIG. 5 (F-2). The output of the fourth filter 7 is a weighted smoothing filter, and the output of the fourth filter 7 is a multivalued image restoration in which halftones are easily preserved, while characters and edges are highly preserved.

The outputs of these two filters 7.8 having different properties are input to the selector 9, and are selected according to the first-order differential signal of the selector 6 to obtain the final output. The selector 9 selects the output of the fifth filter 8 when the first-order differential signal of the selector 6 indicates a character or an edge.

As an alternative to the output of the selector 6 in the above embodiment, after selecting the output of the filter shown in FIG. 4 where S=T for the period T of the binary image according to the PTSEL signal, the output of the filter shown in FIG. 6 (E- The square root of the sum of squares of each output value of the first-order differential filter shown in 1) and (E-2) may be output.

Also, another example of the generation of the PTSEL signal and 1. Well, the seventh
As shown in the figure, a correlation determining section 10 may be provided to obtain the PTSEL signal. Here, the inside of the correlation determining section 10 is
The configuration is shown in FIG. 9 and FIG. That is, this correlation determining section 10 includes three determining sections 20-1 to 20-3.
In the determining section 20-1, the exclusive OR inverting circuit 21
The exclusive OR of the two pixels is inverted, and AND gated with CLK and CLK by the AND circuit 22 to generate a count-up pulse and increment the counter 23a. The output of the exclusive OR inverting circuit 21 generates rlJ only when the two forces match, and increments the counter 23a, so the correlation between the two forces directly becomes the magnitude of the output of the counter 23a.

2 of the exclusive OR inverting circuit 21 of the judgment unit 10 as described above.
Two pixel data (indicated by diagonal lines) having a distance of t as shown in FIG. 10 are inputted manually.

Similarly, the determination units 20-2 and 20-3 have t=3, t=
Two pixels of 2 are input, and the strength of the correlation between the pixels separated by the respective distances is output to the output terminals j1 to j3,
The comparators 23 to 25 determine the size, and the decoder 26
A PTSEL signal is generated according to t with the strongest correlation.

Further, in the first embodiment, the output of the selector 6 is directly input to the selector 9, but a circuit as shown in FIG. 11 may be inserted between them.

That is, in this circuit, 2 lines of the output of the cell 1/actor 6 are input to the 3-person chaor circuit 62 via the 2-line buffer 61, and 1917 minutes are directly input to the 3-person chaor circuit 62.
A total of three lines are input to the three-person chaor circuit 62 in such a manner that the input signals are input to the three-person chaor circuit 62. First, the OR of 3 consecutive pixels in the vertical direction is taken, the latches 63 and 64 delay the horizontal direction by 1 pixel and 2 pixels, and the 3-person OR circuit 65 takes the OR of the 9 pixels in total. Or is taken. In this case, even if an output as shown on the left side of FIG. 12 is obtained from the output of the selector 6, the pixel of interest is ORed and converted from "0" to "1".

Also, if there are more than one ``1'' in a rectangular area of nXm (n, m are natural numbers), the pixel of interest is converted to ``1'' and the other pixels are converted to ``O''. By performing such conversion, it is possible to eliminate erroneous judgments due to noise in the first-order differential, and to widen the judgment area for characters and edges.

[Effects of the Invention] According to the present invention, even if the image to be processed has a periodic structure such as a dither image, an appropriate multilevel image can be restored without being affected by the periodic structure. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image processing circuit according to the present invention. FIG. 2 is a schematic diagram showing the principle of the first to third filters in the first embodiment. Figure fs3 is a circuit diagram showing an example of the circuit configuration of the first to third filters in the rfi1ii embodiment. FIG. 4 is a schematic diagram showing the principle of the fourth filter in the first embodiment. FIG. 5 is a schematic diagram showing the principle of the fifth filter in the first embodiment. FIG. 6 is a schematic diagram showing the principle of a filter used in the second embodiment of the present invention. FIG. 7 is a block diagram showing an image processing circuit according to a third embodiment of the present invention. FIGS. 8 and 9 are circuit diagrams showing the configuration of a correlation determining section provided in the third embodiment. FIG. 10 is a schematic diagram illustrating input pixel data of the correlation determining section in the 1s3 embodiment. FIG. 11 is a block diagram showing a select signal processing circuit added to an image processing circuit according to a fourth embodiment of the present invention. FIG. 12 is a schematic diagram showing how data is converted by the circuit shown in FIG. 11. 1...5 line buffer section. ? ...D flip-flop, 3-5...filtering section, 6.9...selector, 7.8...filter, 21...inverting circuit for discharging OR, 22...AND circuit , 23a...Counter, 23-25...Comparator, 26...Decoder, l, 42...Adder, 3...Subtractor, 4.46...Addition unit, 5...・Latch, 7... Seven pixel delay section, 8... Subtraction section.

Claims (8)

[Claims] (1) Image processing means; Output means for outputting a plurality of differential signals with respect to the image signal to be processed; Selection means for selecting a differential signal; Controlling the image processing means based on the selected differential signal. An image processing device comprising: a control means for controlling; and; (2) The image processing apparatus according to claim (1), wherein the image signal to be processed is a binary image, and the image processing means is a restoration circuit from a binary image to a multivalued image. (3) In claim (1), the selection of the differential signal is such that the center distance between the element for which the kernel component of the differential filter of the differential circuit is positive and the element for which the kernel component is negative is determined with respect to the period of the image signal to be processed. An image processing device characterized in that an output of a matching or closest differential filter is selected. (4) The image processing apparatus according to claim (1), wherein the instruction to select the differential signal is given by a CPU. (5) The image processing device according to claim (4), wherein the image signal is received from another device, and the instruction is given based on data received by a communication means such as a protocol with the other device. . (6) Claim (1) provides that the control of the image processing means selects the output of the smoothing filter having the same or the closest matrix size to the period of the image signal to be processed. Characteristic image processing device. (7) The image processing device according to claim (6), wherein the image processing device switches between the output and another output of the image processing means according to the selected output. (8) The image processing device according to claim (7), wherein the other output is a multi-value restoration circuit using a smoothing filter with a small matrix size that easily preserves edges.