JPH0325252U - - Google Patents

Info

Publication number
JPH0325252U
JPH0325252U JP1989085961U JP8596189U JPH0325252U JP H0325252 U JPH0325252 U JP H0325252U JP 1989085961 U JP1989085961 U JP 1989085961U JP 8596189 U JP8596189 U JP 8596189U JP H0325252 U JPH0325252 U JP H0325252U
Authority
JP
Japan
Prior art keywords
semiconductor chip
view
lead frame
showing
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989085961U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989085961U priority Critical patent/JPH0325252U/ja
Publication of JPH0325252U publication Critical patent/JPH0325252U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5434Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は一実施例を用いて半導体チツプを実装
した状態を示す部分断面図、第2図は同実施例の
部分平面図、第3図は一実施例の製造工程を示す
工程断面図、第4図はインナーリード部がエツチ
ングされた後の金属板を示す図であり、Aは平面
図、Bはその−′線位置での断面図、第5図
は他の実施例を用いて半導体チツプを実装した状
態を示す部分断面図、第6図は従来のリードフレ
ームを用い微細加工された半導体チツプを実装し
た場合を示す平面図、第7図は同従来例の部分断
面図である。 10……リードフレーム、12……インナーリ
ード、14……アイランド、16……半導体チツ
プ、18……ワイヤ。
FIG. 1 is a partial sectional view showing a state in which a semiconductor chip is mounted using one embodiment, FIG. 2 is a partial plan view of the same embodiment, and FIG. 3 is a process sectional view showing the manufacturing process of one embodiment. FIG. 4 is a diagram showing the metal plate after the inner lead part has been etched, A is a plan view, B is a cross-sectional view at the -' line position, and FIG. FIG. 6 is a partial sectional view showing a state in which a chip is mounted, FIG. 6 is a plan view showing a case in which a microfabricated semiconductor chip is mounted using a conventional lead frame, and FIG. 7 is a partial sectional view of the same conventional example. 10...Lead frame, 12...Inner lead, 14...Island, 16...Semiconductor chip, 18...Wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプに対向して配置され、半導体チツ
プのパツドとの間で接続がなされるインナーリー
ドの板厚がアウターリードの板厚より薄くなつて
いるリードフレーム。
A lead frame in which the inner leads, which are placed facing the semiconductor chip and are connected to the pads of the semiconductor chip, are thinner than the outer leads.
JP1989085961U 1989-07-21 1989-07-21 Pending JPH0325252U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989085961U JPH0325252U (en) 1989-07-21 1989-07-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989085961U JPH0325252U (en) 1989-07-21 1989-07-21

Publications (1)

Publication Number Publication Date
JPH0325252U true JPH0325252U (en) 1991-03-15

Family

ID=31635352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989085961U Pending JPH0325252U (en) 1989-07-21 1989-07-21

Country Status (1)

Country Link
JP (1) JPH0325252U (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957439A (en) * 1982-09-27 1984-04-03 Fujitsu Ltd Semiconductor device
JPS628545A (en) * 1985-07-05 1987-01-16 Hitachi Ltd High density lead frame
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device
JPS62177953A (en) * 1986-01-30 1987-08-04 Nec Corp Lead frame

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957439A (en) * 1982-09-27 1984-04-03 Fujitsu Ltd Semiconductor device
JPS628545A (en) * 1985-07-05 1987-01-16 Hitachi Ltd High density lead frame
JPS6248053A (en) * 1985-08-28 1987-03-02 Nec Corp Manufacture of lead frame for semiconductor device
JPS62177953A (en) * 1986-01-30 1987-08-04 Nec Corp Lead frame

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