JPH03253123A - Decoding system for error correcting code - Google Patents

Abstract

PURPOSE:To efficiently execute minimum bit error decoding algorithm and to reduce the capacity of a memory by reusing a working storage area to be used for forward or backward repeating operation again in revesed repeating operation to execute decoding. CONSTITUTION:In the case of applying the minimum bit error decoding algorithm to a linear code obtained by terminating a code word by a certain length, forward repeating operation and backward repeating operation are executed once in each by using only the storage area required for the forward repeating operation. In this case, all calculated results on the way of a decoding process are stored in a decoding operation RAM 112, and at the time of advancing decoding, data are read out from a RAM 112 and the product sum operation between the read data and a branch metric value is executed by a multiplexer 140, an adder/subtractor 141 and an accumulator 122. Thus, the bit error rate can be efficiently reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a system for minimizing the error rate of each decoded information bit on the receiving side for a sequence encoded by an error correction linear encoder and transmitted. The present invention relates to a decoding method for error correction codes.

(Prior art) Conventionally, as one of the methods to effectively remove errors that occur on the transmission path and achieve highly reliable communication, the sending side performs encoding with a certain degree of redundancy, and the receiving side Conversely, there is a method of correcting errors that occur on the transmission path by estimating the information sequence that is determined to have been transmitted on the transmitting side from this encoded received sequence. This is FEC (Forward Error Correct
ion) or forward error correction method.

Encoding methods used in FEC can be broadly classified into block encoding and convolutional encoding. Among these, convolutional encoding is a method in which an information sequence is continuously encoded using a shift register of a fixed length. On the other hand, block encoding is a method in which information sequences of a certain length are encoded as a group. Next, there is a Viterbi decoding method as a typical decoding method for these codes. The Viterbi decoding method is generally applicable to linear codes having a trellis structure, or is currently mainly applied to convolutional codes.

Viterbi decoding is an algorithm that performs maximum likelihood estimation of a state sequence under a finite state discrete-time Markov process in a noisy channel with no memory. Words are always selected. Therefore, in this sense, Viterbi decoding can be said to be the optimal decoding algorithm. Since Viterbi decoding also allows soft-decision decoding to be performed relatively easily, it is currently widely used as an effective decoding algorithm for convolutional codes, mainly in satellite communication systems. This Viterbi algorithm is described in literature (1) (G, D, For
ney, Jr.: “The Viterbi Al
gorithm”, Proc, of IEEE,
Vol, 61. No, 3. pp, 268-278
．． March 1973).

On the other hand, in contrast to Viterbi decoding, which minimizes the error rate as a codeword, there is a decoding algorithm that minimizes the error rate for each symbol or bit that constitutes a codeword (hereinafter this algorithm will be referred to as the minimum bit error decoding algorithm). ). This algorithm will be briefly explained below.

The notation here follows Document (1). The code constraint length is V time k
The transmitted information at Uk+ The state of the encoder immediately before that is X*'' (U k-1+ U k-2+..., U
k-v). Also, the observation sequence on the receiving side from time 0 to k is Z o""(21111211...'!
Z k ), and the corresponding state sequence from the initial state at time 0 to the terminal state at time is expressed as
Or X ++ ”' + X h++).

The likelihood for x o”’ is.

λ(ξ→= InP (X+++ l x+) I
nP (z+ l x+)...(1) It is given as follows.

However, ξ+ = (X++++ X+) represents the transition at time i,
Moreover, P (%) each represents the conditional thrust probability.

It is assumed that the code word is terminated in a certain state X K + 1 immediately after the final time of the coded sequence. The joint probability between observation series z (= z oK) and X during that time is P
(xk, z)=P(xk, zok-')P(zkKlx
k) ・−・(2), which is given by P (xi, zo′−′)::Σ P (L−++ zo′−2)exp(−λ(ξ, −1
)...(4) It is obtained by repeating the calculation. Let S(u,) be the last component of X5,1 at time k or u, EE (o, 1)
Let be a set of states such that . At this time P (um,
z) = Σ P (xm-+, z)k+1 [S(
By calculating (5), we can find the combination probability of information bits U at time o P(um
=0. z)>P(uh=1. If z), then u,=0,
If P(um=0.z)<P(um=1.z), then u
b = L P(u*=0.z)=P(uh=l,
z), decoding is performed by randomly outputting U,=O or um=1. This minimum bit error decoding algorithm is described in Reference (2) (L, R, Bahl.

J., Cocke, F., Jelinek and
J. Raviv: “Optimal Decodi
ng of Linear Codes for Mi
nimizing SymboI Error Rat
e'', IEEE Trans, Inf, Theo
ry, Vol.

IT-20, pp. 284-287. March
1974). The minimum bit error decoding algorithm has the advantage of having the best bit error rate characteristics and being able to provide a measure of the accuracy of the subsequent result for each bit or symbol, but on the other hand, as will be discussed below. However, it has not been used as a decoding method to replace Viterbi decoding because it has some essential drawbacks.

When compared with Viterbi decoding, the disadvantage of the minimum bit error decoding algorithm L is that it requires backward iterative operations in addition to the forward iterative operations necessary for Viterbi decoding during decoding.

Moreover, since the received sequence that is subject to backward repetition operations is always the interval from the time of the bit targeted for decoding to the end of the received word, decoding must always be performed forward and backward after the entire codeword has been received. Calculations must be performed repeatedly. On the other hand, in the case of Viterbi decoding, it is possible to perform decoding using only forward iterative operations. Moreover, since the forward iterative operation can be continued every time a bit or symbol is received, it is not necessary to provide the received sequence all at once, and decoding in continuous mode is possible.

Further, in the case of minimum bit error decoding, there are disadvantages such as a large storage area being required for decoding and a large number of repetitions of product-sum operations being required. For these reasons, Vitahi decoding or especially fIJ is becoming more widely used for decoding convolutional codes.

(Problems to be Solved by the Invention) As mentioned in the section of the prior art, the minimum bit error decoding algorithm requires a large amount of calculations and also requires a very large storage area for decoding. According to literature (2), using a convolutional code with constraint length ■ and coding rate R = ko/no,
If the code length defined on CF (2) is τ, a storage area of 2×2 kOv·τ is required for the forward iterative operation. Further, if the backward repeat operation is performed directly, it will require the same storage area as the forward repeat operation, so a total storage area of only 2×2 kOv·τ is required. For example, the code length is τ=1000 bits, v=6, R=
If 32 bits are allocated to 1/2.1 storage areas, the total storage area will be approximately 4 Mbits, and the load placed on the decoder will be large. Furthermore, when actually performing forward and backward iterative calculations, there is a drawback that it is necessary to change initial processing, steady processing, terminal processing, and the calculation processing thereof depending on the configured trellis.

Next, when actually executing the minimum bit error decoding algorithm, the likelihood is treated as a real value, so multiplication between real numbers is required. As a result, when the block length becomes longer, the possibility that the likelihood value increases or decreases extremely and goes beyond the computable range of the arithmetic unit becomes very high. Furthermore, since this algorithm calculates the joint probability P (um, z) as described above, taking the probability of um=0 and adding the probability of =1 does not result in 1. Therefore, it has the disadvantage that it is difficult to obtain objective reliability from this information alone.

Furthermore, when performing decoding using the minimum bit error decoding algorithm, it is desirable to use an appropriate branch metric for decoding, and to do so, it is necessary to know the transition probability of the channel.

If the state of the communication path is known, there will be no problem, or
If not, assume an appropriate communication channel state, or
Alternatively, information on transition probabilities must be obtained using some other means.

The present invention has been made to solve the problems of the prior art described above, and provides a decoding method for error correction codes that can efficiently reduce the bit error rate.

(Means for Solving the Problems) The system of the present invention for achieving this object has the following features in its configuration.

That is, the first feature of the present invention is that when applying the minimum bit error decoding algorithm to a linear code whose code word is terminated with a certain length, forward The iterative operation and the backward iterative operation are performed once each to efficiently execute the minimum bit error decoding algorithm and to reduce the amount of memory.

A second feature of the present invention is that the maximum posterior probability P (ulz) can be determined by using the reciprocal of the value obtained in the forward iterative calculation as the initial value of the backward iterative calculation.

The third feature of the present invention is to avoid overflow of the arithmetic unit by standardizing the metric table.

A fourth feature of the present invention is to estimate the transition probability of a channel using received soft decision weight information when performing soft decision decoding, and use this information to select an appropriate branch metric.
By using this in decoding operations, the purpose is to perform accurate minimum bit error decoding.

(Structure and operation of the invention) The structure and operation of the present invention will be explained in detail below using specific examples. Note that in the embodiment of the present invention, for simplicity, the encoding rate R=
The following describes a 1/2 convolutional code.

(Embodiment 1) FIG. 1 shows a minimum bit error decoder constructed using the present invention. In the figure, the received soft-decision reception sequence 100 is stored in the reception sequence RAMll0. This stored data is read out as necessary, and an appropriate address of the metric ROM III is accessed through the ROM address calculation unit 142. The value of a branch metric is stored in the metric ROM 111, and an appropriate metric value corresponding to the received data and the branch on the trellis to be calculated is given to the multiplier through the multiplexer 130.

All intermediate calculation results in the decoding process are calculated using the decoding operation R.
It is stored in AM112. When proceeding with decryption,
Data is read from the RAM 112 and multiplied and summed with the aforementioned branch metric values by a multiplier 140, an adder/subtractor 141.
This is done by the accumulator 122.

The calculation results left in the accumulator 122 are stored in the decoding calculation RAM 112, or are used in subsequent product-sum calculations as necessary. Also, accumulator 12
The internal flag of the status register 123 changes depending on whether the contents of 2 are positive or negative. When the final operation result is obtained in the accumulator 122, the status register 123
The contents of the flag are written into the decoding result storage RAM 113. When all the decoding for the received codeword is completed, this stored data is read out and decoded data 101 is obtained.

Next, since the process of actually performing decoding using this decoder is the center of the present invention, this will be described in detail below.

Here, the convolutional code to be decoded has a coding rate R=
1/2 An unsystematic code with a constraint length v=2 is used, and the code word length is L=6 techniques. However, this includes two branches for terminating the code word. FIG. 2 shows a wiring diagram of the convolutional encoder, and FIG. 3 shows a trellis diagram constructed by this encoder.

In FIG. 3, it is assumed that transitions from state to state occur at regular time intervals, and the time of the state immediately before the transition at time t occurs is referred to as state time -.

Each state corresponds to a shift register state of the encoder, and has four states: 00.01110.11. An encoded branch code is shown on the branch. Further, the solid line branch in the figure indicates that the information bit input is 0, and the dotted line indicates that the information bit input is l.

Initial state state time of the calculation RAM 112 for decoding
Table 1.1 shows the configuration and initial state of the minimum bit error decoding arithmetic RAM 112 for decoding. The RAM has a two-dimensional array structure with 2v rows and L+2 columns, and the contents of the RAM in the i row and j column are r(i.

Indicated by j). In the example of the present invention, since V=2 and L=6, 0≦i≦3.0≦j≦7. Also i=0.1.2
．． The encoder state corresponding to 3 is 0O1lO101,1
Set to 1.

Decoding can be broadly divided into forward iterative operations and backward iterative operations.

In the forward iterative calculation, first the calculation RAM 112
After clearing the contents to zero, the state time in the initial state is 0-
Write the probability (1) of state 00 in r (0,0).

This is the situation shown in Table 1.1. Here, the subscript j in the table corresponds to state time j-.

Then, the probability P of the state at state time j- over 1- to 5-
(x+-, zo'-') is calculated as follows until 1≦j≦5, and this is calculated as r' (XI-+j)
be the value of

State time j- State 00: r(0,j)=r'(0,j-1)"λ
+−+(00)+ r (2,j−1)” λ+−+(
11) State 10: r(1, D=r(0, j-1)"
λ+-+(0)+r(2,j-1)"λr-1(oo
) State 01: r(2,j)=r(1,j-1)"
λ, −+(Of)+r(3,j−1)”λ+−1(10
) State 11: r(3,D=r(1,j-1)"λ+
−+(10)+ r (3,j−1)” λt−+(0
1) Here, λr (oo) indicates the branch metric corresponding to the branch with branch code 00 at time j. The above steps are performed in the decoder as follows.

First, the contents of accumulator 122 are cleared.

Next, the received word at time j-1 is stored in the received sequence storage RAM.
It is taken out from ll0 and latched in the ROM address calculation unit 142. Multiplexer 130 is ROMIII
Select the input from .

Second, r is updated for state time j- from state 00 to state 11 as follows.

Taking state 00 as an example, first r' (
0°j-1) is loaded into the fetch register 121.

At the same time, λJ -1 (00) is obtained from the metric ROM III through the ROM address calculation unit 142. At the next timing, the multiplier 140 multiplies the two, and as a result, r(0,j-1)" λ+-+(00) remains in the accumulator 122. At the next timing, r(2,j- 1) and similarly loads it into the register 121.

At this time, λ+-+(11) is simultaneously loaded from the metric ROM III through the ROM address calculation unit 142. At the next timing r' (2, j-1)" λ
+−+(11) is calculated by the multiplier 140, and finally added by the adder/subtractor 141 and stored in the accumulator 12.
2, the value r(0, J 1)" λ+-+ (00) + r (2, J 1)" λ4-1 (11) remains. Finally, this calculated value or r' (0
, j), and the accumulator 122 is cleared. By performing this operation for all states, the calculation for the received word at time j has been completed, and the received word corresponding to time j+1 is then stored in the received sequence storage RAM l.
Take it out from l0 and repeat the same operation.

State time 0- 1- 2- 3- 4- 5- 6 Table 1.2 shows the contents of RAM II2 at the time when the forward repeat operation is completed. The shaded area in the figure is the area where calculations were performed. The fact that 0 is written in the shaded area indicates that the calculation result is always 0. This indicates that initial processing was performed without any special exception handling. Also, no special termination processing is performed, or as shown later, equivalent processing is automatically performed at the end of the backward iterative calculation.

0- 1- 2- 3- 4- 5- 6
The state time is followed by backward calculation. First, an initial value for backward search is set in the calculation RAM 112 by setting I' (0,7) =1. Table 1.3 shows the state of the RAM 112 at this point. Up to 0≦j≦5, the results obtained by the forward iterative calculation are stored. In addition, in the backward iterative calculation, the calculation result of state X, - for state time j- is stored in r' (x+, J+1).

Next, after calculating the probability P (z+51 x+-) of the state at state time j- over 5- to 1- as follows,
Multiply it with the previously calculated P (XI-+ Zo'-') and get P(x+).

Find 2).

State time j- State 00: r' (0, j+1) = r (0, j+2)
” λj (00) + r (1, j + 2)” λ j (11) State 10: r' (1, j + 1) = r (2, j + 2)
” λj (01) + r (3, j + 2)” λ j
(10) State 01: r (2, j+1) = r
(0, j+2)" λj (11) 10 r' (1, j+2
)”λj(OO) state 11: r'(3,j+1)
=r'(2,j+2)"λj(10)+r(3,j+2
)" λj (01) The process of actually performing an operation in the decoder for a certain state time j- is exactly the same as the forward iterative operation, so it will be omitted. When the above-mentioned iterative operation at J- is completed, 1” (XI-+ j) is state X at state time j-
, - forward iterative operation result, r(x+-1J+1)
stores the backward iterated calculation result of state X at the same state time. r' (XI-+ J)"r(x+-,
P (XI-+ Z) is obtained by calculating j+1). After this, the sum of states P (L-, z) in which branches such that the information bit at time j-1 is 0 is connected, and P(x+
−, z), compare the magnitudes of both, and select the one with greater probability to perform decoding at time j−1. By repeating this operation until time 0, decoding of all received words is completed. Here, in the backward iterative operation, at state time 5-, r (2
, 6), r (3°6) becomes 0, and as a result P (
xs=2. z) and P(xs=3.z) are each 0. This indicates that termination processing was performed without any special exception handling. Similarly, P (x
+=2. Z) and P (x+=3. z) also become 0, and the initial processing is also completed.

When using the encoder of this embodiment, as is clear from the trellis diagram of FIG.
The tip of the branch of 0 corresponds to state 10.11, and the tip of the branch of information bit -1 corresponds to state 10.11. That is, in the RAM 112, i=0.2 is at the tip of the branch with information bit=0, and i=1
．． 3 corresponds to the tip of the branch with information bit=1. A practical example of decoding is performed as follows.

First, the accumulator 122 is cleared and the multiplexer 130 is selected as the RAM 112. Load I" (0, j+1) from RAM 112 into register 121. Same as next item <r' (0, 3) from RAM 112
is read out, multiplied with the register 121, and the result is stored in the accumulator 122. Next, RAM1
Load (1, j+1) into the register from 12. Next, read r'(1,j) from the RAM 112,
Multiplication is performed with the register 121, but since this result is a result for the state corresponding to the information bit (2), an operation is performed to subtract the multiplication result from the accumulator 122 by the adder/subtractor 141. Furthermore, for the next state of 1==2, after performing multiplication in the same manner as above, the adder/subtractor 141
The multiplication result is added to the accumulator 122 by . Finally, subtraction processing is performed using the adder/subtractor 141 for the state of i=3. The result of performing these operations is P (uk=
Q, z) P (uh = 1. z). In other words, this is the likelihood of information bit = 1 subtracted from the likelihood of information bit = 0 at time j, and if this value is positive, it is 0, if it is negative, it is l, and if it is 0, it is randomly Or 1 is the decryption result. In this case, the positive and negative information of the contents of the accumulator 122 is stored in the status register 12.
3, so this is stored in the decryption result storage RAM 1.
Write to 13. The above calculation process completes the decoding at time j-1. At this point, the forward iterative calculation result for column j is no longer needed, so it is used as a storage area for the backward iterative calculation at time j-2. This operation,
The storage area is repeatedly used, and when decoding up to time 0 is completed, information in the decoding result storage RAM 113 is finally output as decoded data 101 in response to a request from the terminal.

In this example, fixed initial values are written in the first and last columns of the memory, or these two columns can be omitted by improving the operation. In this case, 2 of the 2v matrix
The present invention can be implemented with a memory having a dimensional array structure.

(Embodiment 2) FIG. 4 is a diagram showing a second embodiment based on the present invention. The difference from FIG. 1 is that the RAM 410 stores the received word.
The soft-decision weight data excluding the MSB is connected to the adder/subtractor 441 through the multiplexer 431, and the calculation result of the accumulator 422 is stored in the register 424. This register 424 has a function of holding a value given to the ROM address calculation section 422.

Further, the metric ROM 411 stores a plurality of metric tables optimized for different transmission path conditions. Table 2.1 shows an example of this table.

Table 2.1 (RAM for E, AO = 0.OdB) Table 2.1 assumes a transmission path where E, /N, (energy per 1 bit in the transmission path/one-sided noise power density) = 0.0 dB. This shows the contents of a metric table ROM for 8-value soft decision. In Table 2.1, the address is 8 bits, of which the upper 2 bits are the decoder or the branch code on the assumed trellis branch, and the lower 3 bits are the 8-value soft decision reception data corresponding to each technique code. .

Table 2.2 (E, /N o = o, odB) Soft decision reception area 0 (011) ], (010) 2 (001) 3 (000) 4 (100) 5 (101) 6 (110) 7 ( 111) Region probability 0.4658 0.1948 0.1591 0.1017 0.0509 0.0199 0.0061 0.0017 For example, when the branch code is 00 and the soft decision reception bits l and 2 are each 000.001, the table Referring to the region transition probability in Section 2.2, the branch metric value is 0, 1017X 0.1591=0.01618.

This value is the original branch metric value.

However, if such a small value is adopted as a branch metric value and the multiplication is repeated, there is a high possibility that the calculation will underflow. Therefore, if all original branch metric values are multiplied by a certain value in advance before decoding, the underflow and overflow problems can be solved. Therefore, if the area probability itself is regarded as a random variable and the average is taken, 0.2936 is obtained in this case. Therefore, if the metric value per received bit is multiplied by 0.2936-' = 3.4060, the average metric increment will be 1, and divergence can be suppressed. Here, in order to normalize the received 2 bits, a value obtained by multiplying the original metric value by 3°40602 = 11.6008 is used as branch metric data. There are various E in ROM411.
, /N, a plurality of such branch metric tables are prepared according to the values.

Next, an outline of the operation will be described based on FIG.

First, the received soft decision reception sequence 400 is temporarily stored in the received word storage RAM 410. As an initial value, the multiplexer 431 is connected to the RAM 410 side, and the contents of the accumulator 422 are reset to 0.

The received data weight information excluding the MSB from the soft decision data stored in the received sequence storage RAM 410 is sequentially input to the adder/subtractor 441 through the multiplexer 431 and added to the contents of the accumulator 422, and the result remains in the accumulator 422. If this calculation is performed on all the received data, the sum of the reception soft decision weights over the reception amount will be obtained in the accumulator 422. This is stored in register 424. The soft decision weight distribution is closely related to the noise state of the transmission path, so the register 42
It is possible to estimate the state of the transmission path from the value of 4.

Upon receiving this information, the ROM address calculation unit 442 selects the metric table that best matches the noise condition of the transmission path from among the groups optimized for a plurality of transmission paths, and provides the ROM address to the ROM 411 .

After this, the multiplexer 431 is connected to the multiplier 440 side. Further, the contents of the register 424 are held until the entire received sequence is decoded.

Thereafter, the decoding operation based on the minimum bit error decoding algorithm is the same as in the first embodiment. In addition, in this embodiment, the transmission path state is estimated from the sum of reception soft decision weights, and then a metric table optimized for the transmission path is selected. When decoding is performed every time each codeword is decoded, overflow and underflow can be effectively prevented by finding the distribution of reception soft decision weights, determining the optimal normalization value from this distribution, and performing decoding. can do.

(Third Embodiment) FIG. 5 shows the configuration of a decoder that uses a minimum bit error decoding algorithm and provides accuracy information when each decoded information bit is set to 0.1. The operation shown in the figure will be explained.

The forward iterative operation and the backward iterative operation yield the forward iterative operation result I'(x+-, j) for state x1- at state time j- and the backward iterative operation result r'(x+, j+1) at the same state time. The steps up to this point are the same as in Example 1. For all Xl-, the above r' (XI-+ J) and r' (x+-2J+
1), the information bit at time j−t is 0.
The sum of states P(x+-, z) in which branches such that In exactly the same way,
P(IJ+-+=1.z) is stored in the RAM 513.

The process of performing product-sum multiplication for this purpose is the same as in the first embodiment. Accuracy information is calculated over all times and stored in RAM.
513, this value is passed to the terminal side as accuracy information 501.

(Example 4) Tables 3.1 and 3.2 are based on the present invention, and using the circuit configuration shown in FIG. This figure shows a fourth embodiment in which the conversion is automatically performed.

State time〇 − − − 0″′ − 1-6 State time The following points will be described about the differences from the third embodiment.In this embodiment, the forward iterative operation is performed at the level of j=6, or at least at the level of r (0,6). Repeat until the value is found.RAM 112 at the time when the forward iterative operation for j=6 is completed
The conditions are shown in Table 3.1. P (z) for r(0,6)
The value of is stored.

Next, from P (z), by performing division, we get 1/P (z
) and store it in r'(0,7). r'(0,
7) is used as the initial value and the backward iterative calculation is started. Table 3.2 shows the state of the RAM 112 at this point. Since the value of j = 6 is unnecessary, this area is used as the work area for state time 5-, and the backward iterative calculation is performed as in Example 3. . As a result, the accuracy information obtained as the decoding result at time j is P(u, , z)/P(z)=P(u
+lz). This means that the sum of the probability that u j = 1 and the probability that u j = 0 is always 1.

Therefore, it is possible to immediately evaluate the reliability of the bit without special standardization or the like. Furthermore, this calculation process does not affect the initial processing and terminal processing of the trellis.

(Application Example) Next, an application example of the present invention will be described. Example 1.2 shows a decoder that determines information bits based on a minimum bit error decoding algorithm, and Example 3 shows a decoder that provides accuracy information when information bits are determined using the same algorithm. Ta. The two can be easily combined. In this case, it is possible to configure a decoder that not only determines the information bit but also includes information on how high the accuracy is regarding the bit. In addition, for the sake of simplicity in this embodiment, only an example of implementation using a time-invariant convolutional code with a coding rate R = 1/2 is shown, or a convolutional code with another coding rate, a time-varying convolutional code, Furthermore, the present invention can be applied to punctured codes in exactly the same way, and the present invention can also be easily applied to linear block codes.

In this way, in the present invention, there are almost no restrictions on the code other than that the code word is terminated. Therefore,
Even in existing communication systems, the present invention can be implemented by simply changing the receiving side equipment without making any changes to the code specifications of the system or the transmitting side equipment.
The present invention can be very easily and smoothly introduced into existing systems.

Furthermore, the error correction decoding method according to the present invention is extremely effective when applied to a minimum bit error decoder of the "double decoding method" which was filed by the same inventor on the same day.

(Effects of the Invention) When the method of the present invention is used, decoding can be performed by simply repeating the same algorithm for all times of the received sequence, which facilitates hardware implementation. Further, the decoding method according to the present invention has a large memory saving effect because decoding can be performed using a single memory, whereas separate memories would normally have to be used for forward iterative calculations and backward iterative calculations. Furthermore, by standardizing the metric table used for decoding, it is possible to suppress the occurrence of register overflows and underflows associated with real number product-sum operations. Furthermore, the present invention has the effect that it is possible to select the metric parameters that best match the state of the transmission path when implementing the minimum bit error decoding algorithm. Furthermore, in the present invention, reliability information P(u, l z) of the decoding result at any time i can be correctly obtained by adding division only once during all decoding steps.

Therefore, erasure determination and soft decision information can be easily passed to subsequent decoders and terminals based on this value. Document (1) shows that the decoder realized by the present invention is a decoder that minimizes the bit error rate under a given received sequence.
clarified by. The implementation of such a decoder is considered to have a great effect on improving communication reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
Figure 2 shows the constraint length ■=2. A block diagram showing an example of a coding rate R=1/convolutional non-systematic encoder, FIG. 3 is a trellis diagram constructed by the encoder of FIG. 2, and FIG. Block Diagram Showing Embodiment FIG. 5 is a block diagram showing a third embodiment according to the present invention. 100...Soft decision reception sequence, 101...Decoded data output, 110...Reception sequence storage RAM, ill...Metric ROM. 112... Decoding operation RAM, 113... Decoding result storage RAM, 120... Address auxiliary register, 121... Multiplier input register, 122... Accumulator, 123... Status register 130 ... multiplexer, 140 ... multiplier, 141 ... adder/subtractor, 142 ... ROM address calculation section, 200 ... information bit input terminal, 210 ... encoding output terminal 1. 211... Encoding output terminal 2. 213...1 time slot delay element, 214...
1 time slot delay element, 15 16 00 01 10 11 12 13 20 21 22 23 24 30 31 40 41 42 50 51 ... Modulo 2 addition circuit, ... Modulo 2 addition circuit, ... Soft decision receiving sequence, ...Decoded data output, ...Received sequence storage RAM, ...Metric ROM. ...Decoding operation RAM, ...Decoding result storage RAM, ...Address auxiliary register, ...Multiplier input register, ...Accumulator, ...Status register, ...Register, ・...multiplexer, ...multiplexer, ...multiplier, ...adder/subtractor, ...ROM address calculation section, ...soft decision weight information (excluding MSB), ...soft decision information (MSB ), 00 01 10 11 12 13 20 21 22 30 40 41 42 ... soft decision reception sequence, ... accuracy information sequence, ... reception sequence storage RAM, ... ROM for metric. ...Decoding calculation RAM, ...Accuracy information storage RAM, ...Address auxiliary register, ...Multiplier input register, ...Accumulator, ...Multiplexer, ...Multiplier, ...Adder/subtractor, ...ROM address calculation section.

Claims (1)

[Scope of Claims] (1) The likelihood calculation on each trellis is performed by a forward iterative operation from a bit with an earlier reception time to a bit with a later reception time, and then a backward iteration operation is performed in the opposite direction, or In an error correction code decoding method that minimizes bit errors by performing the forward iterative operation after performing the backward iterative operation, the working storage area used when performing the forward or backward iterative operation is used to store the working storage area in the backward direction. A decoding method for an error correction code, which is characterized in that it is used again in repeated calculations to perform decoding. (2) A claim characterized in that overflow and underflow of the decoding arithmetic unit are prevented by multiplying and normalizing all elements of the branch metric used in the likelihood calculation by a certain constant value in advance. A decoding method for the error correction code described in item (1). (3) When soft-decision demodulation data for the received sequence is given, the transmission path condition is estimated from the weight information of the received sequence to be decoded, and the standard value is determined based on this estimated value. 3. The error correction code decoding method according to claim 2, wherein overflow and underflow of the decoding arithmetic unit are prevented. (4) When soft-decision demodulation data for the received sequence is given, the transmission path state is estimated from the weight information of the received sequence to be decoded, and an appropriate metric table is selected based on this estimated value. The error correction code decoding method according to claim 1, wherein the error correction code decoding method performs highly accurate decoding. (5) When the forward or backward iterative calculation is completed, the probability of occurrence of the received sequence is estimated, and the reciprocal of this value is used as an initial value to perform the iterative calculation in the reverse direction. 1) Decoding method of the error correction code described above. (6) When the forward or backward iterative calculation is completed, estimate the probability of occurrence of the received sequence, perform the iterative calculation in the reverse direction using the reciprocal of this value as the initial value, and calculate the decoded bits obtained by this. 2. The error correction code decoding method according to claim 1, wherein accuracy information is output.