JPH03254525A - Digital signal processor - Google Patents

Abstract

PURPOSE:To facilitate the control of data write/read by dividing an access unit of one buffer with a word length required for the processing, using each of the divided buffer areas for a read buffer/write buffer to apply data write/ read with only one buffer. CONSTITUTION:A word length (1 word) in the unit of access is divided at least into two by a word length (1 byte) required for the processing. Each of the divided word length is processed by a read buffer 54A and a write buffer 54R. Then in writing the data, the data in the read buffer 54A is protected and the write data is written in the write buffer 54R. In reading the data, after the data in the read buffer 54A is read, the data in the write buffer 54R is transferred to the read buffer 54A. Thus, the control of data write/read is simplified. Moreover, the required capacity of the buffer memory is much reduced more than that of a conventional digital signal processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing device such as a so-called DSP (digital signal processor).

[Summary of the invention]

The present invention provides a digital signal processing device in which the access unit has a buffer with a word length that is twice or more than the word length required for processing. In addition, when writing data, the data in the read buffer is protected and written, and when reading data, the data in the read buffer is read and the data in the write buffer is transferred to the read buffer. The present invention provides a digital signal processing device that can reduce the capacity of a buffer memory used and that can easily control data writing/reading.

3. Detailed Description of the Invention [Prior Art] Generally, when an input digital signal is compressed and transmitted,
A plurality of compressed data compressed within a certain time interval (block) are transmitted, and fixed information (parameters) necessary for the compression within the same block is also transmitted.

For example, a digital audio signal on a so-called CD-1 or CDROM-XA may be processed using adaptive differential PCM (A
Adaptive predictive coding (APC) such as DPCM)
In the case of compressing and transmitting data using ive predictive coding, for example, 28 sample sections (0.741 m5ec as 37.8 kHz sampling) of a digital audio signal are taken as one block, and 28 pieces of compressed data obtained for each block are transmitted. be done. At this time, APC prediction filter information and ranging gain information, which will be described later, are transmitted as fixed parameters necessary for the compression process.

Note that when transmitting these APC filter information and ranging gain information, the same information is transmitted, for example, four times in a row in one block, taking into consideration the importance of the information (difficulty in restoring in the case of missing information). It looks like this.

Here, the ADPC of the above-mentioned digital audio signal
The data compression by M and the transmission of compressed data and parameter data are performed by, for example, an apparatus having a configuration as shown in FIG. Fig. 8 shows a device that compresses (pit reduction) a 16-bit digital audio signal to 8 bits, with 32 bytes (parameter 4).
bytes + 28 bytes of compressed data) is executed in 28 sample sections of one block. Further, adaptive predictive coding such as ADPCM is specifically realized by selecting a predictive filter having characteristics according to the properties of the input signal. FIG. 8 shows, as the simplest example, a device that selects either a zero-order filter or a first-order prediction filter on a block-by-block basis.

That is, in the device shown in FIG. 8, the input terminal 1 has a straight PCM (Pulle
A digital audio signal of the SE Code Modulation signal is supplied. This digital audio signal is, for example, 28 samples (28 words).
Data is stored in buffer memories 11 and 12 in units of blocks. However, the buffer memory 11 includes the zero-order filter (not shown).
Each value of the straight PCM signal via is stored as is. Further, the buffer memory 12 stores the digital audio signal through a one-sample delayer 13 and a multiplier 1.
4 and an adder 15, each value of the first-order differential PCM signal obtained through the first-order differential filter is stored. These straight PCM signals and the first difference PC
The M signal is also transmitted to the prediction and range adaptation circuit 16. In the prediction/range adaptation circuit 16, the maximum absolute value (hereinafter referred to as peak value) in each block of the straight PCM value and the first-order difference PCM value or the value obtained by multiplying this peak value by a coefficient is determined for each block. , APC based on these peaks (+! (or their coefficient multiplication (l[))
Filter information is now available. Specifically, the filter selection information that minimizes the value among each peak value (or its coefficient multiplication value) and the filter coefficient of the selected filter (0th order or 1st order filter in FIG. 8) is obtained.

According to this filter information, the buffer memory 11.1 is supplied to the selected terminal of the changeover selection switch 17.
A switching selection of two outputs is performed. As a result, either the straight PCM signal or the first-order differential PCM signal is selected, that is, the zero-order or first-order filter is selected. The output of this switch 17 is sent to a so-called block floating processing section (or block ranging processing section).

In the ranging process in this processing section, the peak value is 16
The gain that is closest to the maximum positive value in the two's complement representation of bits is found, and the 28 words in the same block are amplified by the found gain using the ranging amplifier (sic) 19, and the quantizer 20 is used to amplify, for example, 8 words. This is done by rounding into bits. At this time, so-called noise shaving is performed by feeding back the rounding noise (quantization error) generated at the end of quantization to the adder 18 via the so-called noise shaper 24.

That is, the 16-bit digital signal input from the ranging amplifier 19 to the quantizer 20 is divided into the upper 8 bits and the lower 8 bits by the quantizer 20, and only the upper 8 bits are taken out and rounded. It is output after processing. Also, the bottom 8
The bits are fed back to the adder 18 via the noise shaper 24 described above. That is, in the a-noise shaper 24, the lower 8 bits output from the quantizer 20 are further
The signal (quantization error) that has been left-shifted (256 times) by bits to 16 bits (quantization error) is passed through an amplifier 21 having a gain (coefficient 2-G) opposite to the gain (coefficient 2G) of the amplifier 19 and a delay device. Noise shaving processing is performed by supplying the signal as a subtraction signal to the adder 18 via a predictor consisting of a multiplier 22 and a multiplier 23. Note that the selected filter information (actually, filter coefficients) is transmitted to the multiplier 23.

Further, the prediction/range adaptation circuit 16 also outputs ranging gain information based on the intra-block peak value of the straight PCM signal or the first-order difference PCM signal, and this ranging gain information is transmitted to each of the amplifiers 19 and 21.
The above-mentioned gains (coefficients 2', 2-a) in the amplifier 19.21 are determined by sending the ranging gain information and filter information to the amplifier 19.21.These ranging gain information and filter information are synthesized by the parameter generation circuit 28 and converted into parameter data. It is now output after the

Note that the above corresponds to a mode that compresses 16 bits of input to 8 bits, but in addition to this, in the CD-1 and CDROM standards, when the mode is to compress 16 bits of input data to 4 bits, for example, 4 bits are compressed. One of the prediction filters (zero-order filter, first-order filter, and two second-order filters) is selected.

[Problem to be solved by the invention]

By the way, the above-mentioned data compression process is usually performed using the so-called D
It is realized in software using an SP (digital signal processor). In this DSP,
One task is executed within 26.46 μsec, and the determined compressed data and parameter data are sent to buffer memories 26 and 27 via write changeover switches 25 and 29, respectively. There is. Here, these buffer memories 26 and 27 are designed so that writing and reading of data can be switched alternately. In addition, the write changeover switches 25 and 29 and the output changeover switch 30 on the output side of the buffer memory 26 and 27 are also provided.
is adapted to perform switching operations in conjunction with writing/reading in the buffer memories 26 and 27. Therefore, for example, when data is written to the buffer memory 1J26 and data is read from the buffer memory 27, the selected terminal 25a of the write changeover switch 25 for compressed data
Then, the selected terminal 29a of the write changeover switch 29 for parameter data is selected, and the compressed data and parameter data are written into the buffer memory 26, and at the same time, the selected terminal 30b of the write changeover switch 30 is selected. The data in the buffer memory 27 is read out and output from the output terminal 2. Conversely, when data is written to the buffer memory 27, data is read from the buffer memory 26. At this time, the switch 25 selects the selected terminal 25b, the switch 29 selects the selected terminal 29b, and the switch 30 selects the selected terminal 30a. Such data writing/Vt output is performed for each block.

That is, in the above-mentioned DSP, in order to transmit compressed data and parameter data, the above-mentioned buffer memories 26 and 27 for writing/reading each 32 bytes (4 bytes of parameters + 28 bytes of compressed data) as shown in FIG. Prepare
Data transmission was performed by alternating between writing and reading for each block. Therefore, in this case, a means for switching the write/read operations for each block is required, and reading must necessarily take precedence, making the switching control complicated. Further, -a, memory access inside the DSP is performed in units of words. Therefore, even if the word length required for actual processing is in bytes, it is converted into words, which is the processing unit mentioned above, and a large amount of buffer memory is wasted. . In other words, since the buffer memories 26 and 27 of a normal DSP are in units of 1 word and 16 bits, the word length required for actual processing is 1 byte and 8 bits as shown in Figure 8. However, the 8 bits are converted to 16 bits (for example, by extending the sign bit) before being written.

Therefore, half of the capacity of the buffer memories 26 and 27 is wasted. As described above, conventionally, it is actually necessary to prepare 32 words for each 32 bytes of writing/reading, which results in a lot of waste in terms of buffer memory capacity and chip size.

Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and it is possible to reduce the chip size by eliminating wasted capacity of the buffer memory, and to reduce the size of the chip by writing/reading data to/from the buffer memory. The object of the present invention is to provide a digital signal processing device that is easy to control.

[Means for Solving the Problems] The digital signal processing device of the present invention has been proposed in order to achieve the above-mentioned object, and the access unit has a word length that is twice or more than the word length required for processing. A digital signal processing device having a buffer that divides the word length of the access unit into at least two parts according to the word length necessary for the processing, and each of the divided parts is used as a read buffer and a write buffer. In addition, when writing data, the data in the read buffer is protected and the write data is written to the write buffer, and when reading data, after reading the data from the read buffer, the data from the write buffer is transferred to the read buffer. This is what I did.

Note that the above shows the operation in advance of writing, but
At the time of advance reading, after reading data from the read buffer, at the time of writing, writing to the write buffer and transfer from the write buffer to the read buffer may be executed.

[Effect]

According to the present invention, one buffer access unit is divided into word lengths necessary for processing, and each is used as a read buffer 9 and a write buffer. Therefore,
Data can be written/output using only one buffer memory.

[Example] Hereinafter, an example to which the present invention is applied will be described with reference to the drawings.

FIG. 1 shows functional blocks of a digital signal processing apparatus according to an embodiment of the present invention.

The device shown in FIG. 1 performs bit compression (bit reduction) on digital signals such as audio in blocks (28 sample sections). is applied.

That is, the digital signal processing device of this embodiment uses the buffer memory 54 in which the access unit has a word length (1 word, 16 bits, for example) that is more than twice the word length (1 byte, 8 bits, for example) required for processing. A DSP 50 having a DSP 50, which divides the word length (l word) of the access unit into at least two parts by the word length (1 byte) necessary for the processing,
Each of the divided sections is used as a read buffer 54A and a write buffer 541, and when writing data, the data in the read buffer 54A is protected and write data is written to the write buffer 54, and when reading data, the read buffer 54A is used as the read buffer 54A. After reading the data of write buffer 54. Read data from buffer 54. It was designed to be transferred to.

Here, a 16-bit digital audio signal (straight PCM signal) is supplied to the input terminal 31. This digital audio signal is transmitted to the signal processing functional block 51. The signal processing function block 51
A compression processing function block 52 compresses 16-bit data of each sample into 8-bit data by block floating processing similar to that shown in FIG.
It is composed of a parameter generation function block 53 that generates parameter data (8 bits) based on the prediction filter information and ranging gain information of the PC. This signal processing functional block 51 performs the noise shaving process in addition to the bit compression and parameter generation described above. These 8-bit compressed data from the compression processing function block 52 and the parameter generation function block 5
The 8-bit parameter data from No. 3 is transmitted to the buffer memory 54, and is subjected to writing, transfer, and subsequent processing.

As described above, the buffer memory 54 includes a read buffer 54^, a write buffer 54 . For example, the upper 1 byte (8 bits) of the buffer memory 54 is used as the read buffer 54^, and the lower 1 byte (8 bits) is used as the write buffer 54. It is divided into Here, during the write operation, 32 bytes of 8-bit compressed data or parameter data for each sample are written into the write buffer 54□. That is, the parameter data is written in the first 4 bytes of the parameter storage area SP of the write buffer 54-, and the compressed data is stored in the remaining 28 bytes of the compressed data storage area SD. Also, during a read operation, the write buffer 54. After the data is transferred to the read buffer 54^, it is read out.

By the way, since the embodiment of the present invention is considered to be applied to a boat fishing SP, the actual access unit of the buffer memory 54 is 1 word and 16 words, similar to that used in a normal DSP. It is in bits. That is, the compressed data or parameter data sent to the buffer memory 54 (or output from the buffer memory 54) is usually expanded by adding a sign bit (sign bit) to the 1-byte 8-bit data. word 1
The data is said to have been converted to 6 bits.

For this reason, in this embodiment, the write buffer 54s and read buffer 54 . In order to realize write, transfer, and read operations in 1-byte units, the following processing is specifically performed.

That is, the operational division of the write buffer 54m and read buffer 541 in the buffer memory 54, and the division of these write buffers 541° and read buffer 54A.
Write → transfer and write → read operations in units of 1 byte and 8 bits are realized by intermediating an accumulator 55 having a so-called barrel shifter function.For example, the write buffer 54A, the write buffer The data succession, transfer, and write processing in 540 has a word length of 32 bits, which is four times the word length (1 byte) required for processing, that is, a word length that is twice the word length (1 word) of the buffer memory 54. This is realized by using an accumulator (ACC) 55 as an intermediary.

Here, data for one sample is written to the buffer memory 54 via the accumulator 55.

The specific operations of transfer and successive transfer will be explained.

First, the operation of data write→transfer and write will be explained using FIG.

In this Figure 2, the 1-byte 8-bit compressed data or parameter data (hereinafter referred to as 1-byte data) is converted into data (hereinafter referred to as 1-word data) obtained by extending the sign bit and converting the byte unit into a word unit. It will be sent to you. However, as will be described later, the sign bit-extended l-word data at this time is sent as data with the sign bit cleared and 0 arranged in the upper 8 bits in the case of a negative number. There is. Therefore, if this l word data is written as it is to the buffer memory 54, the read buffer 54. is 0, write buffer 54
．． The above 1-byte data will be written to (
In FIG. 2(a), the l word data stored in this buffer memory 54 is shifted to the left by 8 bits and loaded into the accumulator (ACC) 55 (FIG. 2(b)).
). However, the most significant byte of the accumulator 55 is arranged with a sign bit and an extension bit by 7-bit expansion, and the least significant byte is all O's. The data loaded into the accumulator 55 is separated into an upper word (16 bits) and a lower word (16 bits). In the separated lower word of which only the lower word is shown in FIG. 2(c), the above 1-byte data comes in the upper byte, and O is in the lower byte. At this time, new 1-word data (sign bit extension is suppressed in the case of a negative number) is sent to the buffer memory 54 ((d) in FIG. 2), and the new 1-word data and the above-mentioned separation are sent to the buffer memory 54 ((d) in FIG. 2). A logical OR is performed with the data of the lower word. That is, the reason why the sign bit extension is suppressed (sign bit cleared) for the l-word data sent to the buffer memory 54 in the case of a negative number is to complete this logical OR operation.

Here, the clearing of the sign bit in the case of a negative number is specifically performed under the following conditions. That is, if yn is one word of newly sent compressed data, then when yn≧0, the upper byte of the one word of compressed data is O. Therefore, logical OR1 calculation with the contents of the buffer memory 54 is performed as is. Also, yn
When <0, the upper byte of the current word data yn is cleared to 0, and a logical OR operation is performed with the contents of the buffer memory 54. However, since the parameter data is not a negative number (0-8), this process is not necessary.

The logical OR data obtained as described above ((in Figure 2)
In e)), the upper byte is the previous 1-byte data, and the lower byte is the new 1-byte data. This logical OR
The data is again written to the buffer memory 54 (FIG. 2(f)). That is, the 1-byte data previously written to the write buffer 54 is stored via the accumulator 55 and then stored in the read buffer 54. The new 1-byte data that is transferred to the write buffer 54. and later supplied is transferred to the write buffer 54. will be written to. As described above, the read buffer 54 via the accumulator 55
．． , Data write in write buffer 51L → transfer,
A write operation is performed.

Next, as shown in FIG. 2, the read buffer 54,
The read operation of 1-byte data written in the write buffer 54b will be explained using FIG. 3.

That is, read buffer 541. Write buffer 54
．． The 1-byte data ((a) in FIG. 3) written in is shifted to the left by 8 bits and loaded into the accumulator 55 ((b) in FIG. 3).
The most significant byte of 5 is an expanded pinpoint by sign bit extension, and the least significant byte is 0, and the upper word and lower word are separated. This upper word is read out,
The lower word is restored to the buffer memory 54 ((c) in FIG. 3). By doing this, one word of data is read out.

Write → transfer, write in Figure 2 as described above, and the third
By repeating the reading shown in the figure, it becomes possible to write and transfer data in the buffer memory 54, and output Vt.

Furthermore, in data writing/reading in the device of this embodiment, specifically, data is written to the write buffer 548 once per sample, and written to the write buffer 54m twice per sample. The data is transferred to the read buffer 54A and then read out. That is, during the read operation, as described above, transfer and read are performed twice for each sample, so it only takes 16 sample periods to read all 32 bytes of the read buffer 54A, and the remaining 12 sample periods are Reading is not performed. In this way, it is possible to output compressed data 32 times in synchronization with the 28 compression processes (main task) per block. In this case, there are various ways to send data, but the more data is sent every - times the main task, the less time the DMA (direct memory access) transfer on the host side will have. If data is transferred 8 times every 7 times, the data transmission interval is 1 usec, and the DTRQN pulse width is 100 nsec, and the host side cannot keep up with the speed. Therefore, in this embodiment, as described above, the main task is Two transmissions are made at one time.

2 and 3 described above are based on the premise that data is written to the buffer memory 54 in advance. This is the write buffer 54. This is to transfer the data to the read buffer 54°. However, the data transmission timing may be reversed, with read-out timing first. In other words, for example, as shown in Fig. 4, if 1 byte of compressed data is written to each sample once and read out twice to each sample at the same time, the compressed data will be written in advance until the 4th time. However, from the 5th time onward, the reading is reversed and the reading takes place first.

For this reason, this embodiment employs an algorithm that does not depend on the order of writing precedence/reading precedence.

That is, as shown in FIG. 5, for example, by comparing the addresses using the read buffer index register ARr and the write buffer index register ^Rw, which indicate the address positions of the read buffer 54^ and the write buffer 54m, the write For example, if the relationship between each index register is ARr <
When it is AR-, writing is preceded, so the above-mentioned writing and transfer/reading processes are performed. On the other hand, when the relationship between the registers is ARr>ARw, reading is preceded, so the data is transferred to the read buffer 54A immediately after the subsequent write process is executed.

Specifically, in FIG. 4, the data write start address is $4 ($ represents a hexadecimal number), the successive write start address is $0, and each address is set to index register A.
It is stored in each memory of dsa4 and dma2 as indirect addressing by R- to Rr. From this,
To determine whether it is a write lead or a successive write lead, it is enough to compare each address.In other words, if the relationship between each address is dm
If a4>dma2, read first, d+wa4≦dma2
In that case, writing first is important.

Therefore, when writing data, for example, dma4 >
If it is dma2, the successive addresses of index register ^Rr are already in index register ^Rw.
Since the write address in the write buffer 54 precedes the write address in the write buffer 54, the
1 data cannot be transferred to the read buffer 54A. Therefore, once data is written to the write buffer 54, it is immediately transferred to the read buffer 54m. In addition, if dma4≦dma2 at the time of data writing, the write address takes the lead and the succeeding addresses follow, so when reading data, the write buffer 54. The data is stored in the read buffer 54A.
will be forwarded to. On the other hand, when reading data, the read buffer 54. is the same as the conventional program.

FIG. 6 shows a flowchart of the address write routine to the buffer memory 54 described above.

That is, in FIG. 6, in order to perform indirect addressing using the index registers ARr, ^R-, the write start address of the write buffer 54m is set in the index register ARw in step S1, and the write start address of the write buffer 54m is set in step S1.
2 for write buffer 54. address of memory dma2
Store in. Further, in step S3, the successive start address of the read buffer 54g is set in the index register ^Rr, and in step S4, the address of the read buffer 54A is stored in the memory daa4. After that, in step s5, the compressed data storage area SD of compressed data is
It is determined whether the write loop (in (n is 0 to 27) has reached 27 or not. When n-27 (-aX), the process advances to step S6; when n<27, the process advances to step S9. , in step S6, the parameter data (filter information, ranging gain information) is combined, and further in step S7
After combining the current and past parameter data in step S8, the write buffer 54. parameter storage area S
The combined parameter data is stored in P.

The process advances from step S8 to step S9. Step S
9, clears the code focus of the compressed data (suppresses code bit expansion) as described above and stores the compressed data in the compressed data storage area SD.
In step SIO, the data of dma2 is loaded into the index register AR-. After that, the addresses are compared in step Sll, and it is determined whether it is a read precedence or a write precedence. If it is a write precedence, step 512 is performed.
, if the reading is precedence, proceed to step S14, step S
12, the above-mentioned write buffer 54. After combining the 1-byte data with the new 1-byte data through the accumulator 55 (synthesizing by logical OR operation) and restoring it in the buffer memory 54, step S1
3, the address of the write buffer 54° is updated and the address is stored in the memory dma2. After that, the process moves to the next block. Further, in step S14, like step S12, 1-byte data is synthesized and restored to the buffer memory IJ 54. Thereafter, in step S15, data is immediately transferred from the write buffer 548 to the read buffer 54A, and in step S15
In step 6, the address of the write buffer 541 is updated, the address is stored in the memory dma2, and processing shifts to the next block.

Here, what has been described above is about encoding (i.e. bit compression) in DSP, but conversely,
In the case of decoding processing in P, access to the buffer memory 54 is the opposite of that described above. That is, as shown in FIG. 7, 2 bytes of data are received from the encoder for each sample and written to the write buffer 54, and 1 byte is received for each 1 sample to the read buffer 5.
4A. In this way, on the decoder side, writing always precedes and reading follows.

As described above, the digital signal processing device of this embodiment divides the access unit of the DSP and uses each as a read buffer and a write buffer, and also has two
By performing address comparison using the index registers of the set, the write and read order can be changed to m! data can be written, transferred, and continued. That is,
During advance writing, the data in the read buffer is protected and written, and during reading, the data in the read buffer is read and the data to be written is transferred from the write buffer to the read buffer. Also, when reading first,
After reading data from the read buffer, writing to the write buffer and transfer from the write buffer to the read buffer are executed immediately. in this way,
In the device of this embodiment, it is possible to substantially divide the buffer memory and access each part independently, and therefore, the capacity can be reduced to 1/2 compared to the buffer memory of a conventional DSP. .

Furthermore, compared to a system that adaptively switches between reading and writing for each block, control is easier because dedicated read buffers and write buffers are used.

[Effects of the Invention] In the digital signal processing device of the present invention, the word length of the access unit is divided by the word length necessary for processing, and each is used as a read buffer and a write buffer, and when writing data, the read buffer is Data writing/reading can be easily controlled by writing data while protecting it, reading data from the read buffer when reading data, and transferring data from the write buffer to the read buffer. Further, the required capacity of the buffer memory can be reduced compared to the conventional one, and therefore, it is possible to reduce the chip size by eliminating wasted capacity of the buffer memory.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing a schematic configuration of a digital signal processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining data write → transfer and write operations, and FIG. 3 is a data read operation. FIG. 4 is a diagram for explaining write advance/read advance, FIG. 5 is a diagram for explaining index register, FIG. 6 is a flowchart during write operation, and FIG. 7 is a diagram for explaining write operation. is a diagram for explaining the operation on the decoder side, FIG. 8 is a block circuit diagram showing a schematic configuration for performing conventional data compression, and FIG. 9 is for explaining the write/read operation of the buffer memory of a conventional DSP. This is a diagram for 50・・・・・・・・・DSP 51・・・・・・・・・Signal processing function block 5
2...Compression processing function block 53
......Parameter generation function block 54...Buffer memory 54^.
・・・・・・Read Buffer 54th Hall・・・・・・
・・・・Light banfa 55・・・・・・・・・・・・
Accumulator 155- Fig. 1 @Include advance/Tsuzuki haiku line Fig. 4 Inch Sois L-Jista's strokes Fig. 5 "70-+ Yard Fig. 6

Claims (1)

[Claims] In a digital signal processing device having a buffer in which the access unit has a word length that is twice or more than the word length necessary for the processing, the word length of the access unit is defined as the word length necessary for the processing. At the same time, each divided part is used as a read buffer and a write buffer, and when writing data, the data in the read buffer is protected and the write data is written to the write buffer, and when reading data, the read buffer is used as a read buffer and a write buffer. A digital signal processing device characterized in that after reading data from the buffer, data from the write buffer is transferred to the read buffer.