JPH03254572A - Picture signal processor - Google Patents

Abstract

PURPOSE:To receive clear reduced and enlarged pictures without the degradation of picture quality by executing compression processing and transmitting after thinning fixed bits in advance from a picture signal in the case of executing the reduction of a picture, making the same bit overlapped at fixed timing at writing to a memory to store the picture signal in the case of executing enlargement and making subscanning speed variable. CONSTITUTION:A clock c1 of the 1/2 speed of a clock (c) is supplied to a line memory 31 in the case of executing the reduction of 1/2. Thus, a picture signal (a) is stored in a form with an even bit thinned. Writing timing to the line memory is set to overlap twice at the pulse neiborhood of the reference clock (c) and to sample in the case of enlarging an original twice and transmitting. Accordingly, the line memory 31 becomes full at the stage that 1024 bits, which are the half of the picture signal (a) from a reading device 1, are inputted and are read out by the count of 2048 bits of a counter 71. Besides, the step frequency of a step motor controller 5 is made 1/2 and a subscanning direction is enlarged twice.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device for reducing or enlarging a recorded image on a recording medium by signal processing in a facsimile transmitter or the like.

In conventional facsimile machines, when performing facsimile communication between common models (various controls and modulation methods are the same), a transmitter with a large paper size, e.g. B-4, communicates with a receiver with a small paper size, e.g. A-4. In such cases, the received image of the receiver may be cut off in the middle, or conversely, the received image may be shifted to one side. Therefore, for example, a method of reducing/enlarging the image signal by using a clock faster or slower than the one used when writing the image signal when reading the image signal from the memory that stores the image signal received in the receiver may be considered. However, simply changing the speed of the read clock from the memory does not improve the transmission efficiency in the case of reduction, and has the disadvantage that the image quality in the main scanning direction becomes rough in the case of enlargement.

The present invention focuses on the fact that when reducing an image between facsimile transmitters and receivers, the number of bits of the image signal read by the transmitting side and the number of bits recorded by the receiving side are different. After thinning out the image, it is compressed and transmitted, and if the image is to be enlarged, the same bits are duplicated at a predetermined timing when writing to the memory that stores the image signal, and furthermore, according to each process, The above-mentioned problem is attempted to be solved by making the sub-scanning speed variable.

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an embodiment of the invention. The reading device 1 shown in FIG. 1 is a self-scanning diode array, and its output is a digital output that has been converted from analog to digital. The selector 2 inputs the image signal from the reading device 1 into two line memories 3I and 3! for each line. are alternately switched by a switching signal e.

These line memories 31 and 3. is a 2048-bit serial-in serial-out S/S shift register. The clock controller 4 outputs the switching signal e of the selector 2, and simultaneously outputs the clock C at the time of reduction or expansion to the line memories 31 and 32. The step motor controller 5 is provided because it is necessary to control not only the main scanning direction but also the sub-scanning direction during reduction or enlargement using signals from the enlargement/reduction controller 6. For example, when reducing by 1/2, the frequency is doubled, and when expanding by 2 times, it is 1 times the frequency.
/2 frequency is given to the step motor. The enlargement/reduction controller 6 changes the clock frequency of the clock controller 4 by a signal from the enlargement/reduction controller 6 when a predetermined enlargement/reduction panel switch is pressed before transmission.

Next, first, the operation of reducing and transmitting a document will be explained with reference to FIG. FIG. 2 is a time chart when a document is reduced to 1/2. From the reading device 1, an image signal a
is transferred to the line memory 31 via the selector 2 according to a constant clock.

Here, line memory 3. The writing timing to the line memory 3. is determined by the clock C, but when performing 1/2 reduction, is a clock C1 with a speed of 1/2 of the clock C.
, the image signal a is stored in a form in which even numbered bits are thinned out as shown in the signal d. Note that the counter 7 counts the number of bits of the image signal a, and the line memory 3 counts up 2048 bits per line.
Read out the information within ゜. At this time, line memory 3
Since the output of 1 is only a thinned out 1024 bits, it goes without saying that the transmission efficiency is significantly improved. Next, the selector 2 is switched by the switching signal e, and while the signal d is being read out from the line memory 31, the image information of the next line is similarly transferred to the line memory 3. is written in. When the image signal of this second line is read by the reading device [1], the step frequency output from the step motor controller 5 synchronized with the clock controller 4 is doubled by the signal from the enlargement/reduction controller 6, and therefore the sub-scanning The direction is also reduced to 1/2 the number of bits.

In the above embodiment, the document was reduced to 1/2, but the clock controller 4 can theoretically reduce the size by any number of minutes. However, due to the characteristics of current diode arrays, the limit for expansion is about 4 times, and for reduction, it is 1/2 to 174 times.
It is normal to double the amount, but the actual range depends on the manuscript. In addition, the timing of thinning in the case of reduction is not only for even numbers, but also for odd numbers or alternately between even and odd numbers.
It goes without saying that it may be 1 bit for every n bits, and can be freely selected depending on the reduction rate.

Next, the case where a document is enlarged twice and sent will be explained using FIGS. 1 and 3.

Even in the case of enlargement, the image signal a from the reading device 1 is sent to the line memory 3 through the selector 2 according to the lock C. will be forwarded to. Here, the writing timing to the line memory is set like clock C2 so that sampling is repeated twice near the pulse of standard clock C. Therefore, the line memory 31 becomes full when 1024 bits, which is half of the image signal a from the reading device 1, is input, and is read out by the counter 71 counting 2048 bits. The subsequent operations are the case of reduction and the case of distance. and,
Contrary to the time of reduction, when the image signal of the second line is read by the reading device 1, the step frequency of the step motor controller 5 is halved by the signal from the enlargement/reduction controller 6, so that the step frequency of the step motor controller 5 is halved. It will be enlarged twice.

Incidentally, the writing timing to the line memory can be freely set according to the enlargement ratio, as in the case of reduction.

As is clear from the above description, in the present application, when reducing an image, predetermined bits are thinned out from the image signal and then compressed and transmitted, and when enlarging the image, the image signal is accumulated. The same bit is duplicated at a predetermined timing when writing to memory, and the sub-scanning speed is varied according to each process, making it possible to receive clear reduced and enlarged images without deterioration in image quality. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the image signal processing device according to the present invention, FIG. 2 is a time chart for explaining the operation when the original is reduced in FIG. 1, and FIG. 3 is when the original is enlarged in FIG. 1. 2 is a time chart for explaining the operation. 1.--.--Reading device, 2.--.Selector, 3. ．． 3. −・−・−Line memory, 4・・・・
-...- Clock controller, 5-... Step motor control 9.6... Enlargement, reduction controller, 7, . 7!・−・・−・Counter.

Claims (2)

[Claims] (1) A reading means for photoelectrically converting image information on a document, a sub-scanning means for moving the document in the sub-scanning direction when the reading means is operated, and a memory for temporarily storing image signals read from the reading means. a transmission means for transmitting the image signal output from the memory; and a transmission means for reducing the number of bits written in the memory than the number of bits read by the reading means in accordance with a reduction command, and reducing the document moving speed of the sub-scanning means. An image signal processing device comprising: control means for performing speed-up control. (2) A reading means for photoelectrically converting image information on a document, a sub-scanning means for moving the document in the sub-scanning direction when the reading means is operated, and a memory for temporarily storing image signals read from the reading means. a transmission means for transmitting the image signal output from the memory; and a transmission means for increasing the number of bits written in the memory than the number of bits read by the reading means in accordance with an enlargement command, and increasing the document moving speed of the sub-scanning means. An image signal processing device comprising a control means for performing slowing control.