JPH0325551A - Memory access method - Google Patents

Abstract

PURPOSE:To attain space saving and high efficiency when attaching an additional part by connecting plural memory units to separate data buses by dividing into the same number, respectively, and performing control whether each data base is connected in parallel or by switching corresponding to an address range corresponding to the number of bits of a processor to which access is performed. CONSTITUTION:RAMs 0-15 that are the memory units are divided into the groups of every eight units, and data terminals D0-15 are connected to the data buses, respectively, and the data buses are connected to the data buses D0-15 and D16-32 of a CPU via a bidirectional bus buffer. Thus, the same memory can be accessed with all the CPUs of 16 bits and the CPUs of 32 bits effectively, and it is not required to re-attach the RAM when the CPUs of different bits are used or to provide a receptacle by securing an excessive space, or to mount the RAM with memory capacity larger than that to be used in advance. Thereby, the space saving in a memory device and the high efficiency when mounting the additional part can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access method in which a memory consisting of a plurality of memory units is selectively accessed by processing devices having different numbers of bits.

[Conventional technology]

In various data processing devices such as personal computers and word processors, two or more processing devices with different bit numbers (16 bits and 32 bits, etc.) can be used, and any one of them can selectively process multiple RAs.
There are devices that allow access to memory consisting of memory units such as M or RAM modules.

An example of a conventional memory access method in this case will be briefly explained with reference to FIG. 4. A plurality of memory units RAMO to RAM23, which constitute the memory 10, are connected to data buses Do to 15 of a CPU, which is a processing device. RAMO
-15 and RAM16-23 connected to D16-31, 16-bit CPU accesses RAMO-15, and 32-bit CPU accesses RAMO-7 and RAM16-23.
I was trying to access it.

Each RAM of this memory 10 is, for example, 256K.
It consists of four dynamic RAMs (DRAMs) with an X4-bit structure.

11 is a programmable logic array (hereinafter abbreviated as rpLAJ) with a built-in multiplexer, and the address A from the address bus of the CPU (not shown) is
1 to 22, a signal from the control bus that indicates whether the CPU bit number is 32 bits/32BIT (automatically becomes "L" by dip switch or by installing a 32-bit CPU), row address strobe signal /RAS, multiplex signal /MUX, and refresh signal /RFSH, and outputs RAM addresses RAO-8 to the address bus of the memory and row address strobe signals /RASO-15 to the control bus.

Further, a column address strobe signal /CAS is directly input to the /CAS terminal of each RAMO-23.

In this specification and drawings, a "/" is added in front of alphanumeric signal names (for example, RAS, CAS, etc.) to represent negative logic, that is, low active signals.

[Problem to be solved by the invention]

According to such a conventional memory access method, 16b
RAMO-15 when accessed by it's CPU
is used, and RAMs 16 to 23 are not used. Also, 32
When accessing by bit CPU, RAMO ~ 7
and RAM 16 to 23 are used, and RAM 8 to 15 are not used. A memory map in this case is shown in FIG.

Therefore, if each RAM is removably mounted on the board using a socket, for example, a 16-bit CPU
When installing a 32-bit CPU option board to the base board, replace RAM8-15 with RAM16-2.
I had to change it to position 3. Therefore, it not only takes time and effort to replace RAM, but also
8 Mbytes for either CPU (RAM16 in Figure 4)
Even though it only uses 1.
Five times as much space was needed.

Also, if each RAM is directly attached to the board without using a socket, it is impractical to replace the RAM, so it is recommended to install 1.5 times the required amount of RAM from the beginning. Therefore, there was a problem in that cost performance was extremely poor.

This invention was made in view of the above points, and the CP
Even if the number of bits of U changes, it will always be the same memory unit (R
The purpose is to save space and improve efficiency when installing options by making the RAM accessible (AM), or to improve cost performance by eliminating the need to install an extra memory unit.

[Means to solve the problem]

In order to further achieve the above object, the present invention uses a memory access method in which a memory consisting of a plurality of memory units is selectively accessed by a processing device with a different number of bits. In addition to connecting to the data bus, each data bus connected to the memory unit is connected in parallel to the data bus of the processing device depending on the number of bits of the processing device to be accessed, or the data buses are switched and connected depending on the address range. It is designed to control data bus connections.

[For production]

According to the memory access method according to the present invention, when a processing device with a large number of bits (for example, a 32-bit CPU) accesses memory, each data bus connecting the same number of memory units of the memory is connected to the data bus of the processing device in parallel. By connecting, all memory units can be accessed in parallel.

In addition, processing devices with a small number of bits (for example, 16 bit
When C P 'U ) accesses the memory, if each data bus on the memory side is switched according to the address range and the data bus on the processing unit side is connected,
All memory units can still be accessed.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing an example of a memory access device for implementing the memory access method according to the present invention.

In this embodiment, the memory 1 is made up of 16 memory units RAMO~15, which are divided into groups of 8 each, and the first group RAM
Each data terminal Do to 15 of 0, 2, 4, 6, 8, 10, 12, 14 is connected to the first data bus RDO to 15, respectively, and the second group of RAMI, 3, 5, 7, 9 . 1
Each data terminal Do-15 of No. 1, 13, and 15 is connected to a second data bus RD16-31, respectively.

These first data buses RDO-15 and second data buses RD16-RD31 are connected to data buses pO-15 of the CPU, which is a processing device, via bidirectional bus buffers 2 or 3, respectively. data bus RD16-3
1 directly connects the 32-bit CPU data bus D16 to D32
It is also possible to connect to Note that each RAMO to 15 of this memory 1 is also a dynamic RAM (DR) with a 256K x 4 bit structure, for example.
AM) Consists of 4 pieces.

4 is a PLA that has a built-in multiplexer similar to the PLA 11 explained in FIG. 4, and it receives addresses A1 to A22 from a CPU address bus (not shown) and a signal indicating whether the number of bits of the CPU is 32 bits or not from a control bus. /3 2B I T, the row address strobe signal /RAS and column address strobe signal /CAS, which are basic timing signals, the multiplex signal /MUX, and the refresh {a number /RFSH} are input.

Then, each RAMO~1 is connected via the memory address bus.
RAM address RAO~8 to address terminal AO~8 of 5
/RA of each RAM via the control bus.
S terminal 8-row address/S1-lobe signal/RASO~7
(corresponding two RAs of the first and second groups)
give the same /RAs for M).

Furthermore, A1 of addresses A1 to 22 from the CPU
The signal /CASL that becomes "L" when 9 is "L" and A1
Outputs a signal /CASH that becomes "L" when 9 is "H". /CASL is the first group RAM0.2.4,6,
/CA to each /CAS terminal of 8, 10, 12, l4
S H is RAMI of the second group, 3, 5.7, 9,
11, 13, and 15 at the same time, /CASL is a bidirectional pass buffer 2.
/CASI{ is also input to one input terminal of a NAND gate 5 whose output terminal is connected to the enable terminal G of the bidirectional pass buffer 3.

/32BIT signal is the CP that accesses this memory.
This is a signal that determines whether U is 16 bits or 32 bits,
When this number a/32BIT is "L", the CPU is 32B
it, and when it is ゜H゛, the CPU is 16 bits.

If the CPU of the base port is 16 bits and the CPU of the option board is 32 bits, a circuit like the one shown in FIG.
and pulled-up pin 61] and option board 7
Two bottles 7a, 7b connected by side short 11B
This can be determined by the signal /32BIT becoming "L" as a result of the combination.

In addition, PLA4 uses CP when this /32BIT is "H".
It is determined that U is 16 bits, and the signal /16BIT is set to ``L'', and it is input to the other input terminal of the NAND game 1-5.

Furthermore, although not shown in FIG. 4, the read signal /R
OE and write signal/RWE (one of them becomes ゜L゜, but not both become ゛L゛ at the same time) are connected to each RA.
Input to /OE terminal or /WE terminal of MO~15 and connect to each RA.
Specify data read/write to M, read signal /RO
E also manually connects the direction specifying terminals DIR of the two bidirectional pass buffers 2 and 3 to switch the data transmission direction.

Here, the operation during memory access according to this embodiment will be explained.

First, we will explain the case where a 16-bit CPU (not shown) accesses memory 1 as a processing device.
The data buses DO to 15 of bitCPU are connected to the data buses DO of each data input/output terminal A of bidirectional pass buffers 2 and 3.
~15, and nothing is connected to the data buses RD16 to RD31 of the second group of RAMs in the memory 1.

At this time, the signal /32BIT input to the PLA4 is FF, so the signal /16BIT output from the PLA4 becomes "L", which activates one input of the NAND gate 5. Among addresses A1 to 22 from the CPU, when A19 is "L", it is output from PLA4 /C
Since ASL is at ``L'' and /CASH is at ``H'', the bidirectional pass buffer 2 becomes ready for data transmission because the enable terminal G becomes ``L'' by /CASL.
On the other hand, /CA-SH is ゛H゜, so NAND gate 5
Since the output of the bidirectional pass buffer 3 becomes ゛H゜, the enable terminal G becomes ゛H゜, so that the bidirectional pass buffer 3 enters a cut-off state.

Therefore, when the address is *ooooo~N7FFFF, the data bus Do~15 of the CPU is connected only to the data bus RDO~15 of the first group RAM, and the 16-bit CPU is connected to the data bus RDO~15 of the first group RAM0,
By accessing 2, 4, 6, 8, 10, 12, and 14 according to the address, it is possible to read required data or write data to a designated address.

When A19 in the address from the CPU is ゛H゜, /
Since CASL becomes "H" and /CASH becomes "L", the bidirectional pass buffer 2 becomes cut off because the enable terminal G becomes "H" due to /CASL. On the other hand, when /CASH becomes "L", the output of the NAND gate 5 becomes "L", so that the bidirectional pass buffer 3 becomes ready for data transmission because the enable terminal G becomes "L".

Therefore, at addresses soooo to IFFFFF, the CPU's data buses Do to 15 are connected only to the RAM data buses RD16 to RD31 of the second group, and the 16-bit CPU is connected to the RAM's data buses RD16 to RD31 of the second group.
AMI, 3, 5, 7, 9, 11, 13.15 can be accessed according to the address.

Next, a case where a 32-bit CPU (not shown) accesses the memory 1 as a processing device will be explained.
The data buses DO-15 and D16-31 of U are connected to the buses DO-1 of each data input/output terminal A of the bidirectional path buffer 2.3.
15 and the second group RAM data bus RD16 to RD3.
1 respectively.

At this time, the signal /32BIT input to the PLA4 is "L", so the signal /16BIT output from the PLA4 becomes "H", and one input of the NAND gate 5 becomes "H", so what happens to the other input? Regardless, its output becomes ``H'', and the enable terminal G of the bidirectional pass buffer 3 is always kept at ``H'', thereby cutting it off.

Therefore, data bus Do~15 of 32bjtCPU
is always the first group RAM data bus RDO~15
Then, D16 to 31 are connected in parallel to the data buses RD16 to RD31 of the second group of RAM, respectively, and the 32-bit CPU uses the first group of RAM and the second group of RAM, which constitute memory 1, as addresses. 1 depending on
You can read the required data or write data to a specified address by simultaneously accessing them one by one.

In other words, all RAMOs ~ 15 can be accessed in parallel, two at a time, and if this is made into a memory map, the third
The result will be as shown in the figure.

In this way, according to this embodiment, the 16-bit CPU and 3
A 2-bit CPU can access all of the same memory without wasting it, so when using a CPU with a different bit number, you can replace the RAM, secure extra space for it and provide a socket 1, or change the amount of memory used. There is no need to install the above RAM in advance.

Therefore, it is possible to save space in the memory device, improve efficiency in attaching options, and improve cost performance.

Similarly, by applying the memory access method of this invention, 16-bit CPU, 8-bit CPU, 32-bit
It is also possible to effectively access all of the memory units (RAM) that make up the memory by using various CPUs with different bit numbers, such as a tCPU, a 16-bit CPU, and an 8-bit CPU.

〔Effect of the invention〕

As explained above, according to the memory access method of the present invention, even if the bit number of the processing unit (CPU) changes, all the same memory units (RAM) that make up the memory can always be accessed, so extra space and Eliminates the need for sockets or extra memory units;
It is possible to save space, improve efficiency when installing options, and improve cost performance.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an example of a memory access device for implementing the memory access method according to the present invention, and FIG. 2 is an explanatory diagram showing an example of means for detecting attachment of an option board to the base board. , FIG. 3 is an explanatory diagram of the memory map according to the embodiment of FIG. 1, FIG. 4 is a block circuit diagram showing an example of a memory access device applying the conventional memory access method, and FIG. 5 is an illustration of the memory map. It is an explanatory diagram. 1... Memory 2, 3... Bidirectional path buffer 4... Programmable logic array (PLA.
) 5...NAND gate 6...Base port 7
...Option board RAMO~15...Memory unit

Claims (1)

[Claims] 1. In a memory access method in which memory consisting of a plurality of memory units is selectively accessed by processing devices with different bit numbers, the plurality of memory units are divided into the same number and each is connected to a separate data bus. and data bus connection control for connecting each data bus to which the memory unit is connected in parallel to the data bus of the processing device according to the number of bits of the processing device to be accessed, or switching and connecting the data buses according to the address range. A memory access method characterized by performing the following.