JPH0325643A - Disk controller - Google Patents

Abstract

PURPOSE:To obtain a disk control unit to show equal throughput to each host device by defining the storing area of a data block, which is stored earliest out of data buffers, as the storing area of the requested data block when there is no idle area for storing the data of the newly requested data block. CONSTITUTION:Data buffers 114-117 arranged corresponding to host devices 101-104 in order to store the data read out of a disk device and being sources for sending the data to the correspondent host devices 101-104, a storage control means 113 provided corresponding to the host devices 101-104 in order to define the storing area of the data block, which is stored earliest out of these data buffers 114-117, as the storing area of the requested data block when the contents of these data buffers 114-117 are blocked by the data of the data block, which is former requested from the host devices 101-104, and there is no idle area for storing the data of the newly requested data block are provided. Thus, such a trouble that the rate of the data block existing in the data buffer is different from each central processor and the throughput of the disk device is different is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a disk control device, and particularly to a disk control device connected to a plurality of central processing devices.

[Conventional technology]

Conventionally, this type of disk control device is connected to a plurality of central processing units 101, - 104 via a host ink 7 ace bus 105, as shown in the block diagram in FIG. The data button and command 1a are sent and received between the terminals 104 and 104. Interface circuit 10
6 is host interface 7 ace bus 105, control circuit 307
and the buffer readout control circuit 309, and transmits the information 3b on the host interface bus 105 to the control circuit 307, and conversely, receives the data path connection instruction signal 3C from the control circuit 307. It has a function of sending data from the readout control circuit 309 to the host interface bus 105.

The control circuit 307 is a circuit that receives the information 3b on the host interface bus 105 sent from the interface circuit 106, extracts the command, request block address k, and host number, and controls the overall operation of the disk controller 313. be. That is, the address management circuit 30
The request block address 3d of the host is sent to 8, and the request block address 3d received from the buffer address management circuit 308 is sent to
If the content of the block presence/absence signal 3e indicates "request block present", the data path connection instruction signal 3C is sent to the ink 7 ace circuit 306; if the content indicates "request block, no data path", the disk dedication control is sent. Read command 3 to circuit 312
It has the function of sending f. The buffer address management circuit 308 inputs the request program address signal 3d from the control circuit 307 and checks whether the data of the request program already exists in the data buffer 310. The content of the request program presence/absence signal 3C sent to the circuit 307 is set to "request program, program present", and if it does not exist, the content of the request program, program presence/absence signal 3e is set to "request program, program absent". If it is set to "request pro, ku", the data buffer 3 in which the data of the request pro, ku exists for the buffer readout control circuit 309.
10 and an activation signal for transferring read data 3j from data buffer 77310 to interface circuit 106. When set to "no request program", a signal 3h consisting of an activation signal for transferring data 3e from the disk read control circuit 312 to the data bar 77310 and a data write address is sent. Further, when receiving the 1 write completion signal 3m from the write control circuit 311, the requested program address is registered as existing in the data buffer 310, and then a registration completion signal 3m is sent to the control circuit 307. do. The data buffer 310 is a buffer that stores data from the disk device. Buffer loading control circuit 31
1P disk reading, data 3l from control circuit 312
This circuit receives the data buffer address and transfer start signal from the address management circuit 308 and performs write transfer to the data buffer 310. Also, after the 4F write transfer to the data buffer 310 is completed, a write is made to the address management path 308. 0 disk read control circuit 3 1 2 #'i. Generates control signals necessary for reading data from the disk device.
is sent to the write control circuit 311.

In such a conventional disk control device, central processing unit #. The process in which the data of the requested program address is sent to the central processing unit R101 by a read command from the data server 101 will be explained with reference to cases where the data already exists in the data server 310 and cases where the data does not exist. First, when data of the requested block exists in the data buffer 310, a read command button and request program address 3b are sent from the central processing unit mioi to the control circuit 307 via the host interface bus 105% interface circuit 106. The control circuit 307 analyzes the sent command D and the request program, and sends the buffer address management circuit 30
Sends request pro and quad address 3d to 8. The buffer address management path 308 checks whether the data of the sent request program address exists in the data buffer 77310, and if it exists, the content of the request program presence signal 3e is changed to "request block address". It is sent to the control circuit 307 as "Yes". The control circuit 307 sends a data path connection instruction signal 3c to the interface circuit 306 when the content of the request program presence/absence signal 3e is "request program presence/absence". The buffer address management circuit 308 sends the address where the requested program data exists to the buffer read control circuit 309, and then sends a transfer operation activation signal to send the read data 3j from the data buffer 310 to the interface circuit 106. Sends out 3g. The buffer read control circuit 309 sends the buffer data of the received address to the interface circuit 106, and the data is sent to the central processing unit 101 via the host interface path 105. Next, if the data of the request program address from the central processing unit 101 does not exist in the data buffer 310, the above-mentioned processing is performed until the command command and request program address from the central processing unit 101 are sent to the control circuit 307. I know it. The control circuit 307 analyzes the sent command p and the request program address, and sends the request program address 3d to the address management circuit 308.
Fi.08 checks whether the data of the requested block address sent by Fi. The content of the requested program presence/absence signal 3C is returned to the control circuit 307 as "no requested program". Furthermore, the buffer address management circuit 308 sends a signal 3h containing the storage address of the read data and a write transfer start signal to the buffer address write control circuit 311, and the buffer address management circuit 308 sends the signal 3h containing the storage address of the read data and the start signal of the write transfer to the buffer address write control circuit 311.
Wait for l. The control circuit 307 controls the disk read control circuit 3 according to the signal from the buffer address management circuit 308.
A request block read command 3f is sent to the request block 12. The disk read control circuit 312 is a disk device request processor,
The sent data 3l is written to the data buffer 310 by the buffer write control circuit 311. When the buffer write control circuit 311 completes the transfer operation,
Write completion signal 3m to the buffer address management circuit 308
Send out. Upon reception of the write completion signal 3m, the buffer address management circuit 308 transfers the requested program address sent from the control circuit 307 to the data buffer 30.
After registering as existing within 0, a registration completion signal 3n is sent to the control circuit 307. The bar, 7 address management circuit 308 further sends the data storage address in the data buffer 310 to the bar, 7 a read control circuit 309 from the data storage address in the data buffer 310 and the activation signal for the transfer from the data bar, 7-r3 1 0 to the interface circuit 106. It sends out a signal 3g.

Upon receiving the registration completion signal 3n, the disk control circuit 307 sends a data bus connection instruction signal 3C to the interface circuit 106. The buffer read control circuit 309 sends the read data 3K from the data buffer 310 to the central processing unit 101 via the interface circuit 106.

Next, how to determine the data storage address when the data of the requested block from the central processing unit is not in the data bar 77310 and needs to be newly read from the disk will be explained. FIG. 4 is a diagram illustrating the access order and contents of the data buffer 310 having data for eight programs as a data buffer. Fourth
In the figure, reference numeral 401 indicates the order in which data blocks were requested within the same central processing unit, and the smaller the number, the earlier the requests were made. Reference numeral 402 is the number of the central processing unit that requested the contents of the data block. Reference numeral 403 is a number indicating the order of requests for read commands from the central processing unit, and the smaller the number, the more recently the read commands have been executed. Reference numerals 404 and 405 indicate ba and 7 a blocks. Figure 4 f
a) is the central processing unit fi for the disk control device 313;
101, 102, 103, 104, 104, 102, 1
The data buffers 7 requested in the order of 02 and 103 are all filled with data. If there is a third read request from the central processing unit 103 in state (a), and the requested program address is different from the first and second requests, the bar, address management circuit 308 will send the address to the 41st address ( b)
As shown in FIG.
Assigned as the second data address. As a storage address for a new request block, the block used by the most recent request at the time of the request is assigned. In this state (b), central processing unit #.
When a read request for the same request block as the data in the buffer block 405 in (a) comes from the buffer block 101, since there is no data in the data buffer 310, it is necessary to perform a read operation from the disk device by the above-mentioned step 11m. come.

Therefore, the central processing unit 101 requires a longer time than in case (a) to obtain the data of the requested block. In this way, if the degree of access to the disk control unit 313 varies depending on the central processing unit, the central processing unit with high access frequency can access data at high speed.
As a result of this, access to the pond's central processing unit becomes slow.

[Problem to be solved by the invention]

As explained above, in the conventional disk control device, ′!
By allocating storage addresses in the data buffer to each request program, if there is no free space, the program to be erased is determined based only on the request order, and therefore, depending on the access frequency of the central processor. The ratio of request programs in the data buffer varies depending on the central processing unit.
The first problem is that the processing capabilities of the disk devices differ from the perspective of each central processing unit. Furthermore, in a central processing unit such as another central processing unit that has low access frequency, even if the same data block is accessed repeatedly, it is necessary to read data from the disk each time, resulting in a second problem that processing performance is extremely reduced.

[Means to solve the problem]

In response to a disk data read request from a host device, the disk control device of the present invention checks whether there is a requested data block in the data buffer, and if there is, the data of the requested data block that exists in the data buffer is transferred, and if there is not, the disk control device checks whether the requested data block exists in the data buffer. is a disk control device connected to a plurality of host devices that reads data of a requested data block from a disk device and sends the obtained data to each host device.
A data buffer is provided corresponding to the host device that stores read data from the disk device and sends the data to the corresponding host device, and the contents of this data buffer are the data previously requested by the host device. If a block is blocked by data and there is no free space to store the data of a newly requested data block, the storage area of the oldest data block in this data buffer will be used to store the data of the requested data block. and a storage control means provided corresponding to the host device serving as the storage area.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of one embodiment of the present invention.

In FIG. 1, central processing units 101 to 104 are host devices connected to disk controllers 111, 1, and 9, and a host interface bus 105 is used to exchange data and commands between the host devices and disk controllers l1!3. This is the bus that will take you there. The interface circuit 106 is connected to the host interface bus 105, the control circuit 107 and the read control circuit 112, and the host ink 7.
Sends the information 1b on the ace bus 105 to the control circuit 107, and conversely sends the data 1f from the buffer read control path 112 to the host interface bus 105 by receiving the data bus connection instruction signal IC from the control circuit 107. It has a function. The control circuit 107 takes as input the information 1b on the path sent from the P/A 7 Ace circuit 106, extracts the command, request program, quad address k, and host device number, and controls the overall operation of the disk control device 119. It is a circuit. That is, the address management circuit 10
It sends a signal 1d including the host device's request program, quad address, and host device number to 8-111, and receives a solicitation block, que presence/absence signal 1e>, and registration completion signal lx from the buffer address management circuits 108-111. Further, when the content of the request program, block presence signal 1e indicates "request program, block presence", a data bus connection instruction signal IC is sent to the interface circuit 106. If the content of the request program presence signal 1e indicates "no request program, program", after sending the read command to the disk read control circuit 118,
By receiving the registration completion signal 1z from the address management circuits 108 to 111, the interface 7 ace circuit 106
A data bus connection instruction signal IC is sent to the data bus connection instruction signal IC. The buffer address management circuits 108 to 111 receive a signal 1d consisting of the requested program address and the host device number from the control circuit 107, and respond from the buffer address management circuits 108 to 111 according to the name of the host device. This circuit selects the 0 and 7 address management circuits and checks whether the requested program data exists in the data buffer corresponding to the host device number. If the data exists in the data buffer, the content of the request program presence signal 1e is sent to the control circuit 107 as "request program, program presence";
7A For the read control circuit 112, the buffer number (data number for selecting the one corresponding to the host among 7A 114 to 117), the transfer source address of the data including purple, and the start signal for the 7A read transfer. A signal 1g consisting of If the data does not exist in the data buffer, the content of the request program presence signal 1e is sent to the control circuit 107 as "no request program, program", and then the buffer write control circuit 1
A signal (any one of Ik to 1n) consisting of a data storage address including the No. 13 and No. 7 numbers and an activation signal for reading data 1x from the disk device is sent to the puffer write control circuit 113. Signals 1k to 1n are bidirectional signals that also include a write completion signal from buffer write control circuit 113. Upon receiving the write completion signals 1k to 1n from the buffer write control circuit 113, the buffer address management circuits 108 to 111 that have sent out "request program, no block" output "request program, no block". ” is internally registered as existing, and a registration completion signal 1z is sent to the control circuit 107. In addition, bat 7
Signals 1g to 1j including a data buffer address including a buffer number and a read transfer activation signal are sent to the data buffer read control circuit 112.

7A readout control circuit 112 is the output transfer control circuit. Receives signals 1g to 1j consisting of a buffer address including a buffer number and a read transfer activation signal from the buffer address management circuits 108 to 111, and transfers signals 1g to 1j to the specified buffer address.
The interface circuit 106 sends the data lo to 1r of the forward address to the interface circuit 106.

The buffer write control circuit 113 transfers the read data IX from the disk read control circuit 118 to the data buffer 113.
This is a control circuit that performs write transfer to 4-117. Data server, 77114-117tf corresponds to the host device number,
This is a data buffer for storing data from a disk device. The disk read control circuit 118 is a circuit that receives a data read command from the control circuit 107, reads data from the disk device, and supplies the read data to the buffer write control circuit 113.

Next, in the embodiment, data of the request program is sent to the central processing unit t101 by a read command from the central processing unit t101.
The process up to being sent to O1 will be explained in two cases: a case where the data of the request program exists in the database 7, 114, and a case where it does not exist.

The data of the request program has already been stored in the central processing unit 101.
The case where the data exists in the data buffer 114 will be explained. A read command and request block from the central processing unit 101 via the host interface path 105 and the interface circuit 106 and the quad address 1b are sent to the control circuit 107.
sent to.

The control circuit 107 analyzes the received command and request program, and sends the address management circuits 108 to 111.
Sends a signal 1d containing the central processing unit number "101 (the number on the drawing is the central processing unit number) J> and the request program and quad address to the central processing unit number l'-
Since it is 101J, the buffer address management circuit 1
The seven buffer address management circuits 108 from 08 to 111 are selected. The buffer/7 address management circuit 108 takes in the requested pro/quad address and checks whether data of the pro/quad address exists in the data buffer 114 for the central processing unit number rioxJ. If the buffer address management circuit 108 exists, the buffer address management circuit 108 returns the requested block presence/absence signal 1e to the control circuit 107 as "requested block present", and further sends the buffer address management circuit 108 to the buffer read control circuit 112 the buffer address management circuit 107 in which the data exists. A signal 1g consisting of a number, an address, and a read transfer start signal is sent. On the other hand, the control circuit 107 sends a data bus connection instruction signal 1c to the interface circuit 106 since the content of the request program presence/absence signal 1e is "request program presence/absence". As described above, the data of the request programs of the central processing unit 101 is read out from the data buffer 114 and the signals i o, 1 f, 1
aL: 7) Host interface bus 10 in IIi order
5 to the central processing unit 101.

Next, a case will be explained in which the data of the request program does not exist in the database 7T. The read command and request program from the central processing unit 101 are sent to the control circuit 107, and the address management circuit 108 is selected.
The process up to the time when the server address management circuit 108 receives the requested program address is the same. If data at the requesting program address does not exist in the data buffer 114 for the central processing unit 101, the buffer address management circuit 108 controls the content of the requesting program presence signal 1e as "no requesting program," 0 control circuit 10 sending to circuit 107
Upon receiving the request block presence/absence signal 1e with the contents of "request program, no block", block 7 sends a request program, evening read command to the disk read control circuit 118. In addition, the puffer address management circuit 108 allocates an address in the data bar 771 1 4 that stores read data from the disk device, and sends a signal 1k containing the address and a start signal for write transfer of disk data to the data bar 771 1 to the write control circuit 108 . 113. Data 1x from the disk read control circuit 118 is stored in the data buffer 114 as described above. When the write transfer to the buffers and 7a is completed, the buffer write control circuit i13 transfers the data to the buffer address management circuit 1
08 is notified of the write completion signal 1k. The buffer address management circuit 108 is the buffer write control circuit 11.
Upon receiving the write completion signal 1k from the controller 3, the request program address which was assumed to be non-existent is internally registered as existing, and a registration completion signal 1z is sent to the control circuit 107. Furthermore, the address in the data buffer 114 assigned to the read control circuit 112 for storing read data from the disk, the address in the data buffer 114 indicating the data buffer 114, and the address from the bar, 7a. A signal ig consisting of a read transfer activation signal is sent. Control time M107
In response to receiving the registration completion signal 1z, the data bus connection instruction signal 1c is sent to the interface circuit 106. As described above, the data of the request programs of the central processing unit 101 is read from the disk device and sent to the central processing unit 101 via the data buffer 114.

Next, referring to FIG. 2, a description will be given of how the contents of the data buffers 114 to 117 corresponding to each host device change in response to read commands from a plurality of hosts. FIGS. 2(a) and 2(b) are diagrams showing changes in the contents of the data buffers. To simplify the explanation, each data buffer in FIG. 2 is assumed to have two data blocks.

In FIG. 2, the symbol 201 indicates the order of requests from the same central processing unit, the symbol 202 indicates the number of the central processing unit corresponding to FIG. 1, and the symbol 203 indicates a read request to the disk controller kll9. The numbers 204 and 205 indicate the order, and the smaller the request, the older the request. Chikazu, (a)
button to switch from the central processing units 101 to 104 to the central processing units 10l, 102, 102, 103, 104, 104, 1.
When a read request is made in the order of 03, the data of the requested program and quad address of each central processing unit is stored in the data buffer corresponding to the central processing unit, as shown in the figure.

Next, when the eighth read request is issued from the central processing unit 102, the buffer address management circuit 109 does not fill the data buffer 115 allocated for the central processing unit 102, and the request processor Check if the data exists,
If it does not exist, the server 205 is assigned as the read data storage server 7 from the disk device. FIG. 2(b) shows the contents of the data buffers 114-117 after the data of the eighth request program is stored in the buffer 205.

After this, if the ninth read request is issued from the central processing unit 101 and the requesting program and quad address are the same as the first requesting program and quad address of the same central processing unit, this is different from the case of conventional disk control devices. Since the data in the data buffer is not erased by a read request from another central processing unit, it can be immediately transferred to the central processing unit.

In this way, even if a central processing unit other than the central processing unit 101 frequently makes read requests, as long as the next request program from the central processing unit 101 is the same as the previous request program, the disk device The data can be transferred to the central processing unit at high speed without having to be read from the central processing unit. However, even if each block in this embodiment is realized by software-like means,
It is clear that this does not impair the effects of the present invention.

〔Effect of the invention〕

As explained above, in the disk control device of the present invention, irrespective of the frequency of read requests from the host, data that has already been read into the data buffer 7 may be lost due to the difference in the frequency of read requests with other host devices. The first effect is that a disk control device that does not disappear and exhibits the same processing capacity for each host device can be obtained. Furthermore, there is a second effect that even if a host device receives read requests less frequently than other hosts, it is possible to obtain a disk control device that does not suffer from extreme reduction in processing capacity due to the influence of other host devices.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
and (b) are diagrams showing examples of changes in the data contents of the data buffer 7 in FIG. 1, FIG. 3 is a block diagram of a conventional disk control device, and FIGS. FIG. 7 is a diagram showing an example of changes in the data contents of the data buffer 7 of FIG. 101. ~104...Central processing unit, 105.
...Host interface bus, 106...
...Inter 7 ace circuit% 107,307...
・Control circuit, 108, ~ 111, 308... Bar, 7 address management circuit, 112, 309...
B, 7 A read control circuit, 113, 311...
Buffer write control circuit, 114. ~117.310・
...Data buffer, 118,312...
・Disk read control circuit, 119, 313...
・One disk controller.

Claims (1)

[Claims] In response to a disk data read request from the host device,
It is checked whether there is a requested data block in the data buffer, and if there is, the data of the requested data block that exists in the data buffer is read, and if there is not, the data obtained by reading the data of the requested data block from the disk device is sent to the host device. In a disk control device connected to multiple host devices, a data buffer is provided corresponding to the host device that stores read data from the disk device and is a data source for sending data to the corresponding host device. If the contents of the data buffer are blocked by the data of a data block previously requested by the host device and there is no free space to store the data of the newly requested data block, the oldest data stored in this data buffer will be used. 1. A disk control device comprising storage control means provided in correspondence with a host device that sets a storage area for a requested data block as a storage area for a requested data block.