JPH0325878B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a data forward/inversion circuit for a semiconductor memory in which the physical state and logical state of memory cell data are required to match. .

[Technical background of the invention]

In non-volatile memories such as EPROM (ultraviolet erasable and rewritable read-only memory) and EEPROM (electrically erasable and rewritable read-only memory), the physical state and logical state of memory cell data must match. A requested erased state in which, for example, no charge is accumulated in the floating gate of a memory cell transistor is determined as data "1". Such non-volatile memory,
For example, if the open bit line method is adopted for EPROM, the area around the column sense amplifier will have a configuration as shown in FIG. That is, a bit line BL is connected to a latch-type differential sense amplifier SA in an open bit line manner, and one bit line BL is connected to a large number of memory cells MC (only one is shown in the figure). ) and one reference cell RC are connected, and similarly, the other bit line is also connected to a large number of memory cells MC... and one reference cell RC, and these are connected to the word line WL.
Selected by... Reference numeral 50 denotes a data normal rotation/inversion circuit for maintaining or inverting the logic level of the sense amplifier SA output data, and the output data is sent to the data output terminal 5 through the output buffer 51.
2. The above data normal rotation/inversion circuit 5
0, a transfer gate ₅₃ whose gate is controlled by a control signal A0 applied when selecting a memory cell on the bit line BL side is connected between the input terminal and the output terminal, and an inverter circuit 54 is connected between the input and output terminals. and a transfer gate 55 whose gate is controlled by a control signal ₀ applied when selecting a bit line side memory cell are connected in series.
PR is a bit line precharge/equalization circuit, which includes transfer gate _Q1 for precharge and
It consists of _Q2 and a transfer gate _Q3 for equalization, and a precharge pulse _φPR is applied.

Next, the operation of the memory having the above configuration will be explained with reference to FIG. First, a bit line precharge pulse φ _PR is generated in synchronization with the change in address switching, and the bit line precharge pulse φ PR is generated.
The equalization circuit PR precharges and equalizes the bit line BL. At the same time, the sense latch signal φ _L becomes inactive, and the latch of the sense amplifier SA is released. After the above precharging is completed, the memory cell on the bit line BL side
MC (or memory cell MC on the bit line side) and reference cell RC (or bit line BL) on the bit line side.
The reference cell RC) on the side is selected, and the potential of the bit line BL starts to drop in accordance with the respective conductance (free running state). After a certain time, the sense latch signal _φL becomes active, and by this time the bit lines BL,
The potential difference occurring between BL is sense-amplified and latched by the sense amplifier SA.

Note that the conductance of the reference cell RC is larger than the conductance in the "1" state (erased state) of the memory cells MC, but smaller than the conductance in the "0" state (written state).

By the way, when the memory cell MC on the bit line BL side is selected and the "1" state is sensed, and when the memory cell MC on the bit line side is selected and the "0" state is sensed, the sense amplifier SA
The output data of will be the same. Therefore, in order to make the physical state and logical state of memory cell data correspond, the output data of the sense amplifier SA is directly converted by the data normal rotation/inversion circuit 50 according to the left and right address selection of the sense amplifier SA. It needs to be passed through or reversed.

In the open bit line method described above, the parasitic capacitance of the bit lines is equal on the left and right sides of the sense amplifier, so it is possible to sense relatively small potential differences between the bit lines. This is advantageous for high-capacity, highly integrated memories.

[Problems with background technology]

By the way, the above-mentioned memory has the following problems. After the address changes, the timing from word line selection to the output response of the sense amplifier SA is not necessarily the same as the timing until the gate control input signal A ₀ or ₀ is applied to the data forward/inversion circuit 50. isn't it. Therefore, the timing t ₁ of the gate control input signal A ₀ or ₀ is earlier than the output response of the sense amplifier SA.
, the data output of the data normal rotation/inversion circuit 50 is inverted once, and then the sense amplifier SA
The output data level reaches the normal output data level at the timing t ₂ of the output change. Conversely, if the gate control input signal A ₀ or ₀ changes at a timing t ₃ that is later than the output response of the sense amplifier SA, the output of the data forward/inversion circuit 50 changes at the timing t ₂ of the output change of the sense amplifier SA. once changed and further said timing
The normal output data level is reached at t ₃ . In this way, the pulse-like changing waveform generated in the output of the data normal rotation/inversion circuit 50 appears at the data output terminal 52 via the output buffer 51. This data output terminal 52
Usually drives a large-capacitance load such as a bus line, and the pulse-like changing waveform described above generates a large current, and the peak of this large current causes a noise component in the memory power supply line. This may lead to memory malfunction.

In addition, especially in open bit line memory, it is necessary to charge and equalize the bit line BL with a precharge pulse φ _PR before selecting a memory cell, and during this precharge period, the sense amplifier The output of SA is always at a certain logic level. Therefore, in the worst case, the output data obtained at the data output terminal 52 from the precharge period to the sense amplification period becomes a complex waveform with many amplitude changes, inducing noise pulses in the power supply line, and thereby causing the precharge. There is a possibility that a feedback occurs in which a charge pulse is erroneously generated, resulting in malfunction of the memory.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and
The object of the present invention is to provide a semiconductor memory that can perform normal rotation/inversion processing on the sense amplifier output so that unnecessary amplitude changes do not occur in the data output, and can improve the reliability of memory operation.

[Summary of the invention]

That is, the present invention has an open pit line method or a folded bit line method, and in order to match the physical state and logical state of memory cell data, the sense amplifier output data is rotated in the normal direction and the sense amplifier output data is
In a semiconductor memory having a data normal rotation/inversion circuit for inverting data, the data normal rotation/inversion circuit is
a delay circuit to which a first control signal indicating which of the bit line pairs to select a memory cell connected to is input; and a sense amplifier to which a second control signal is applied to select the memory cell. The state is kept inactive until the output data is unstable. During this inactive state, the first control signal is inputted by the delay circuit, and the sense amplifier output data when the memory cell is selected is kept in the inactive state. After the unstable period of
A logic circuit that controls normal rotation/inversion operation of data becomes active by a control signal, and the output of the logic circuit is latched, and output data of the previous logic circuit is output during the period when the logic circuit is in an inactive state. It is equipped with a flip-flop circuit to
The above logic circuit is characterized in that the unstable period of sense amplifier output data when selecting a memory cell is controlled to a disabled state (non-output state).

As a result, during the period when the sense amplifier output data is unstable when memory is selected, the output data of the flip-flop circuit that latches the previous output data remains unchanged, so unnecessary amplitude changes in the data output are prevented. This eliminates the risk of malfunctions due to the generation of noise, and improves the reliability of memory operations.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Figure 1 uses the open bit line method.
A part of the EPROM is shown, and the data normal rotation/inversion circuit 10 is different from the configuration described above with reference to FIG.
Since the other parts are the same, the same reference numerals as those in FIG. 5 are used, and the explanation thereof will be omitted. The data normal rotation/inversion circuit 10 receives a control signal A ₀ representing address selection on the left (or right) side of the sense amplifier SA.
The output data of the sense amplifier SA and the output of the delay circuit 11 are inputted to a delay circuit 11 that delays the input by a predetermined amount, and when the control signal φ _L ' becomes active, exclusive OR processing is performed and the result is output. , an exclusive OR circuit 12 which is disabled when the control signal φ _L ' is inactive, and a flip-flop circuit 13 which latches the output of the exclusive OR circuit 12.

Next, the operation of the above configuration will be explained with reference to FIG. The operation from the address change to the latch operation of the sense amplifier SA is the same as that of the conventional example shown in FIG. At this time, in the data normal rotation/inversion circuit 10, the control signal φ _L ' is in phase with the sense latch signal φ _L and becomes inactive (low level in this example) at the same time, so that the control signal φ L ' is in the inactive state (low level in this example) and is exclusive during the precharge period and free running period of the bit line. Since the logical OR circuit 12 is disabled,
The flip-flop circuit 13 does not change, and the circuit output 14 remains in the state before the address change. Then, the latch sense signal φ _L becomes active, and the sense amplifier SA performs a latch operation.
When the output data S becomes stable and input to the exclusive OR circuit 12, the control signal φ _L ' becomes active. That is, the control signal φ _L ' is set to become active with a delay of a certain time Δt compared to the latch sense signal φ _L. Also, as the address changes, the control signal A ₀ is output to the delay circuit 11.
, here we receive a delay of some time td,
Before the latch sense signal φ _L becomes active, a delay control signal A ₀ ' is generated and input to the exclusive OR circuit 12. Therefore, when the control signal φ _L ' becomes active, exclusive OR processing is performed and its output is latched by the flip-flop circuit 13, so that when the delayed control signal A ₀ ' is present, The "1" and "0" of the output data S of the sense amplifier SA are respectively inverted and output as "0" and "1" respectively, and the delay control signal A ₀ ' is output. Sense amplifier if not present
"0" and "1" of the output data S of the SA are outputted at their logical levels (non-inverted state, normal rotation state). That is, the normal rotation/inversion operation of the data normal rotation/inversion circuit 10 is switched in accordance with the selection of the left and right addresses of the sense amplifier SA, so that the physical state and the logical state of the memory cell data correspond to each other.

According to the operation of the data normal rotation/inversion circuit 10 as described above, the data output remains unchanged until the control signal φ _L ' becomes active, and the data output remains unchanged when the signal φ _L ' becomes active. is updated (the logic level may remain the same in some cases), and the data output level transitions only once in the worst case (that is, when the logic level is inverted due to the above data output update). Since the output does not include unnecessary amplitude changes, malfunctions of the memory due to these unnecessary amplitude changes do not occur, and the reliability of memory operation is improved.

In addition, the data normal rotation/inversion circuit 10 is
An example of a configuration using a CMOS (phase correction isolated date type) circuit is shown in FIG. That is, the delay circuit 11 is formed by connecting CMOS inverters 31 and 32 in series, and connecting a capacitor 33 between this connection point and the Vss potential (ground potential). The two-input exclusive OR circuit 12 includes CMOS inverters 34 and 35.
and N channel enhancement type MOS transistors N ₁ to N ₇ and P channel enhancement type
MOS transistors P ₁ to _{P 5} are connected as shown. Furthermore, the flip-flop circuit 13 is
CMOS inverters 36 and 37 are connected in antiparallel.

According to the above CMOS circuit, when the control signal φ _L ' is in an inactive state, the N-channel transistor
N ₁ and N ₇ are turned off, and the output "1" of the inverter circuit 35 turns off the P channel transistors P ₂ and P _5.
is also turned off. Therefore, even if the output data S of the sense amplifier SA becomes an intermediate potential between logic levels "1" and "0" as the bit line potential changes during the precharge period, no through current will flow through the CMOS circuit. , it becomes possible to reduce power consumption.

It should be noted that the present invention is applicable not only to the open bit line method as in the above embodiment but also to a semiconductor memory employing a folded bit line method, an example of which is shown in FIG. That is, a plurality of memory cells MC... and one reference cell RC are connected to mutually adjacent bit lines BL, which are connected in a folded manner to the sense amplifier SA, and these are connected to each other in a corresponding manner. Selected by word line WL... In this case, when the memory cell MC on the bit line BL side is selected, the reference cell RC on the bit line side is selected, and conversely, when the memory cell MC on the bit line side is selected, the reference cell on the bit line BL side is selected. RC is selected. Then, the control signal A ₀ corresponding to the selection of the memory cell MC on one bit line (for example, BL) and the output data S of the sense amplifier SA are transferred to the data normal rotation/inversion circuit 10 similar to the embodiment described above. be guided and processed.

〔Effect of the invention〕

As described above, according to the semiconductor memory of the present invention, the sense amplifier output can be normally rotated or reversed so that unnecessary amplitude changes do not occur in the data output, and the reliability of memory operation can be improved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a data forward/inversion circuit in a semiconductor memory of the present invention, FIG. 2 is a timing waveform diagram showing a read operation of the memory shown in FIG. 1, and FIG. 3 is a diagram similar to that shown in FIG. FIG. 4 is a circuit diagram showing another embodiment of the present invention, and FIG. 5 is a circuit diagram showing a data normal rotation/inversion circuit in a conventional semiconductor memory. The circuit diagram shown in FIG. 6 is a timing waveform diagram showing the read operation of the memory shown in FIG. SA...Sense amplifier, BL,...Bit line,
MC...Memory cell, RC...Reference cell, A ₀ ...
Control signal, 10... Data forward/inversion circuit, 11
...Delay circuit, 12...Exclusive OR circuit, 13
...Flip-flop circuit.

Claims (1)

[Scope of Claims] 1. It has an open bit line method or a folded bit line method, and in order to match the physical state and logical state of memory cell data, which bit line of a bit line pair is selected. Depending on whether the sense amplifier output data is
In a semiconductor memory having a data normal rotation/inversion circuit that performs inversion, the data normal rotation/inversion circuit performs a first control indicating which bit line of the bit line pair to select a memory cell connected to. a delay circuit to which a signal is input; and a second control signal to keep the sense amplifier output data in an inactive state until an unstable period of the sense amplifier output data when selecting the memory cell has passed; Data normal rotation/inversion operation in which the first control signal is inputted by a delay circuit and becomes active by the second control signal after an unstable period of sense amplifier output data when selecting the memory cell has passed. and a flip-flop circuit that latches the output of the logic circuit and outputs the output data of the previous logic circuit during the inactive state of the logic circuit. . 2. The semiconductor memory according to claim 1, wherein the logic circuit is an exclusive OR circuit of the sense amplifier output data and the control signal.