JPH0325941U - - Google Patents
Info
- Publication number
- JPH0325941U JPH0325941U JP8376689U JP8376689U JPH0325941U JP H0325941 U JPH0325941 U JP H0325941U JP 8376689 U JP8376689 U JP 8376689U JP 8376689 U JP8376689 U JP 8376689U JP H0325941 U JPH0325941 U JP H0325941U
- Authority
- JP
- Japan
- Prior art keywords
- cycle time
- circuit
- program data
- output
- output circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005259 measurement Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は第１図の動作を説明するためのタイミングチヤ
ートである。
１……ＲＯＭ、１ａ……特定アドレス、３……
アクセス回路、５……許可回路、１２……ＯＲゲ
ート、１３……ＡＮＤゲート、１４……ＩＲ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. 1. 1...ROM, 1a...specific address, 3...
Access circuit, 5...Permission circuit, 12...OR gate, 13...AND gate, 14...IR.
Claims (1)
定アドレスをアクセスするアクセス回路と、 マイクロコンピユータのサイクルタイムを測定
するための測定モード信号に基づき、前記プログ
ラムメモリの特定アドレスが前記アクセス回路で
アクセスされるのを許可する許可回路と、 前記測定モード信号に基づき、各サイクルタイ
ム毎に所定のプログラムデータを出力する第１の
出力回路と、 前記クロツク信号と前記プログラムメモリの特
定アドレスのプログラムデータに基づいて該プロ
グラムメモリの出力が変化した時、前記第１の出
力回路から出力される所定のプログラムデータを
インストラクシヨンレジスタに印加する第２の出
力回路とを備え、 前記マイクロコンピユータが動作可能な最小の
サイクルタイムを測定することを特徴とするマイ
クロコンピユータのサイクルタイム測定回路。[Claims for Utility Model Registration] An access circuit that accesses a specific address of a program memory based on a clock signal; and an access circuit that accesses a specific address of the program memory based on a measurement mode signal for measuring the cycle time of a microcomputer; a first output circuit that outputs predetermined program data at each cycle time based on the measurement mode signal; and a first output circuit that outputs predetermined program data at each cycle time based on the measurement mode signal; a second output circuit that applies predetermined program data output from the first output circuit to an instruction register when the output of the program memory changes based on the program data; A microcomputer cycle time measurement circuit characterized by measuring the minimum operable cycle time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8376689U JPH0325941U (en) | 1989-07-17 | 1989-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8376689U JPH0325941U (en) | 1989-07-17 | 1989-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0325941U true JPH0325941U (en) | 1991-03-18 |
Family
ID=31631708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8376689U Pending JPH0325941U (en) | 1989-07-17 | 1989-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0325941U (en) |
-
1989
- 1989-07-17 JP JP8376689U patent/JPH0325941U/ja active Pending
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