JPH03260839A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the current consumption in response to the task executing performance with a microcomputer which carries out successively plural tasks in time division by providing a task NOP instruction execute neither task and discontinuing the working of a task executing function for a designated period via the task instruction. CONSTITUTION:The n-bit task number data are successively stored in an executing task control memory 101 in the order of execution for the identification of (m) pieces of tasks. The n-bit data includes at least one code to identify a task NOP in addition to the codes corresponding to the task numbers. The code corresponding to the task NOP is decoded by a NOP deciding circuit 103. This decoding result is identical with the task NOP, the reading operation of a microprogram storing memory 105 is tentatively stopped so as to secure a waiting state where the current consumption is reduced. Simultaneously, the output of a microinstruction reading register 106 is kept invalid for a prescribed period. Thus it is possible to reduce the current consumed by a function circuit whose working is stopped.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a microcomputer capable of executing multiple tasks, and more particularly to a microcomputer that can achieve the execution speed performance required by a user in each task and is suitable for reducing power consumption in accordance with the speed performance. .

[Conventional technology]

Conventionally, microprocessors capable of executing multiple tasks include, for example, Japanese Patent Publication No. 1-23812 and Japanese Patent Application Laid-Open No.
-99546, and the 37th Information Processing Society of Japan (Showa 63
Pages 123 to 124 of National Conference Lecture Proceedings (late 2013)
Discussed on page. On the other hand, a so-called NOP instruction is known as an instruction for disabling the execution of arithmetic operations by a microcomputer. This N
The OP instruction is an instruction that is effectively equivalent to not executing any instruction in the execution of arithmetic operations by a microcomputer. Therefore, the execution step specified by the NOP instruction is apparently skipped.

[Problem to be solved by the invention]

In the above conventional technology, even when executing a NOP instruction, N
It is necessary to read the NOP instruction from the memory in which the OP instruction is stored.According to the inventors' study, the current required to read the memory is usually large, which means that the NOP instruction does not perform any calculations. However, it has become clear that the current consumption does not decrease much even if the NOP instruction is executed. Furthermore, in the execution of multiple tasks, when the number of tasks to be executed is small and the task execution speed can be slow, the above conventional technology sets the optimal task execution speed to achieve the required execution performance, and There is a problem in that power consumption cannot be controlled (reduced) according to the execution performance. An object of the present invention is to provide a microcomputer that can reduce current consumption according to task execution performance.

[Means to solve the problem]

The above purpose is to provide a task NOP instruction that does not execute any task in a microcomputer that sequentially executes multiple tasks in a time-sharing manner, and to stop the functional operation of executing tasks for a predetermined period when this task NOP instruction is specified. This is achieved by More specific examples include stopping the reading operation of a memory device that stores a program for task execution for a predetermined period, or stopping the output of the memory device regardless of the data read from the memory device. It has means for fixing to a value that disables the functional operation of a circuit for executing a program.

[Effect]

In the present invention, in a microcomputer that sequentially executes multiple tasks in a time-sharing manner, a task NOP instruction that does not execute any task can be set when determining which tasks are to be executed in what order. That is, any number of task NOPs can be set at any location within the task execution sequence. Therefore, the number (period) of task NOPs is adjusted according to the execution performance required for each task, and the frequency at which each task takes its turn to be executed is
It is possible to control the frequency appropriately according to execution performance. When a task NOP instruction is specified as described above, the functional operation of each functional circuit related to task execution is stopped for the necessary period, and the output of the functional circuit is fixed to a value that does not affect the results of the arithmetic processing up to that point. do. 1. Therefore, the current consumed by the functional circuit whose operation is stopped can be reduced during the period when the functional circuit is stopped.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a microcomputer that can sequentially execute multiple tasks in parallel in a time-sharing manner. In FIG. 1, a task execution sequence is stored in an execution task control memory 101. Each task is identified by a task number, and the tasks corresponding to the task numbers read into the execution task reading register 102 are selectively and sequentially executed. The address management register file 104 holds microaddresses for the microprogram storage memory 105 corresponding to each task in registers corresponding to each task. The microaddress is generated by selectively reading the register corresponding to the task number based on the task number read into the execution task reading register 102. The detailed operation will be explained later with reference to FIG. The microinstruction of the execution task read out from the microprogram storage memory 105 is stored in the microinstruction reading register 106, decoded by the instruction decoder 107, and then executed by the arithmetic execution unit 108. The next address generation unit 109 generates an address corresponding to the next microinstruction to be executed from the operation result 110 and the contents of the next address designation field of the microinstruction. This next address is address management register file 1
It is written to the register of the task corresponding to No. 04, and read out the next time it is the task's turn to execute it. The execution task control memory 101 stores n-bit task number data for identifying m tasks in order according to the order of execution. This n-bit data includes the code corresponding to the task number, as well as the task NOP
Contains at least one code for identifying. The code corresponding to this task NOP is task NOP
It is decoded by the determination circuit 103. The result is task NOP
If so, the reading operation of the microprogram storage memory 105 is temporarily stopped to enter a standby state with low current consumption, and the output of the microinstruction reading register 106 is disabled for a predetermined period. This invalidation means that the output code of the invalidated register 106 does not change the internal state such as the contents of the register at that time. Namely. The instruction execution result after the invalidation period is effectively the same as if there was no invalidation period. Next, the details of the operation of the address management register file 104 shown in FIG. 1 will be explained using FIG. 2. A register 201 stores the microaddress of each task, and has a bit length necessary as an address for the microprogram storage memory shown in FIG. 1, and has registers for the number of tasks. Selection at the time of reading and writing to the register 201 is performed based on the task number read out to the execution task reading register 102 in FIG. That is, in FIG. 2, the task number is decoded by the decoder 202, and the read selector 203 reads out the contents of the register corresponding to the task number. Further, the task number is delayed and held by the delay circuit 206 until a microaddress to be executed next for the task is generated, and after being decoded by the decoder 207, the write selector 208 selects a register to write the address. Further, it is assumed that all address registers 201 are reset to O as an initial state when the present microcomputer is reset. The address data read from the read selector 203 is input to the all'''O' determination circuit 204. a
The “0” determination circuit 204 selects the selector 205 so that if all the input address data is O, the address data is treated as a microaddress; otherwise, the task number that selected the address data is output as it is as a microaddress. control. That is, the start address of each task is the respective task number. Next, the operation of the address management register file when the content read into the execution task read register 102 of FIG. 1 is a task NOP will be described. First, the code corresponding to task NOP is set so as not to correspond to any task number. Therefore, write selector 208 does not select any address register and the contents of the address register do not change for the required period of time. Further, the decoder 202 is configured to select one of the address registers in order to prevent the output of the read selector from going into a high impedance state. At this time, the microprogram storage memory 105 in FIG. Since the reading operation is stopped and the device is in a standby state, the microaddress can be any value. Next, an example of a task execution sequence and pipeline control will be described using FIG. 3. The execution pipeline is 1
It consists of the following six stages. Namely, execution task reading (TRD), execution task decoding (TDC), program reading (PRD), program decoding (
PDC), program execution (PEX), and next address write (AWT) stages. Hereinafter, the stage names will be described using the abbreviations in parentheses above, and the operation of each stage and the connection relationship between each stage will be explained in comparison with the configuration of the microcomputer shown in FIGS. 1 and 2. In the TRD stage, the task number is read from the execution task control memory 101 shown in FIG. 1 and stored in the task number reading register 102. At the TDC stage, the task number is decoded by the decoder 202 in FIG.
04 and selector 205 as a micro address. On the other hand, the task number is task N in FIG.
The OP determination circuit 103 determines whether the task is NOP. In the PRD stage, if the task is not NOP, the microprogram is read from the microprogram storage memory 105 in FIG. 1 based on the microaddress and stored in the microinstruction reading register 106. However, in the case of task NOP, no read operation is performed and the output of the microinstruction read register 106 is invalidated. At the PDC stage, the instruction decoder 107 decodes the microprogram. At the PEX stage, the arithmetic execution unit 108 executes the microprogram. In the AWT stage, based on the execution result 110 of the microprogram, the next address generation unit generates a microaddress for the next execution of the task, and
It is stored in the address register corresponding to the task via the write selector 208 in the figure. At this time, the task number is held by the delay circuit 206 with a delay of three stages PRD and PDClPEX. Above is the pipeline control of each stage. At reset, task number read register 10 in Figure 1
By forcibly setting the output of 2 to the code corresponding to the task NOP, each pipeline stage after TRD can all be kept in the task NOP state. By doing so, it is possible to prevent each stage from malfunctioning after the reset is released. Also, during normal operation, by forcibly setting the output of the task number read register 102 in FIG. 1 to the code corresponding to the task NOP, a task can be executed at any time and for any period of time. Can be temporarily stopped. That is, by filling the task NOP while sequentially executing tasks without destroying the information remaining in the pipeline stages after TDC, it is possible to transition to a temporary stop state while maintaining the internal state. - In the operation after the reset is canceled, the task NOP state is sequentially transferred to the execution state when the information of the task to be executed reaches each pipeline stage, similar to the operation after the reset is canceled. FIG. 4 shows an example of a task execution sequence. FIG. 4(a) shows TOlTl, T2. A case is shown in which tasks T3 and T4 are repeatedly executed in this order. In this case, a task is executed in any time slot, and the microprogram storage memory 105 shown in FIG. 1 is accessed each time to read the execution command, regardless of the program contents in each task. On the other hand, in FIG. 4(b), the task To is executed in only one time slot among the five time slots, and all the others are task NOP. Therefore, the number of times the microprogram storage memory 105 in FIG. 1 is accessed is as follows. This is one-fifth of the case shown in FIG. 4(a). Therefore,
The current consumed when reading the microprogram storage memory can be reduced to one-fifth. Next, with reference to FIG. 5, means for reducing the read current of the microprogram storage memory at the time of task NOP will be explained. There are several specific methods for reducing this current, such as those described below.
In the figure, these are shown together. Therefore, it is necessary to keep in mind that it is sufficient to implement at least one of the following specific measures, and it is not necessary to implement all of them. First, a task NOP signal 500 indicating that the task is NOP is used to deselect the memory cell 508 in the memory mat 510 of the memory. That is, by applying the task NOP signal 500 to the decoding circuit 507 in the X-address decoder 506, the word line 511 is brought into a non-selected state. By doing so, it is possible to eliminate the current flowing through the memory cell 508 during reading. The second means is to turn off the Y-switch 512 by applying the task NOP signal to the circuit 505 of the Y-address decoder. That is, by electrically disconnecting the data line 509 connected to the memory cell selected by the word line 511 from the sense amplifier 501, the data line 509 connected to the memory cell selected by the word line 511 is electrically disconnected from the sense amplifier 501.
09 can be eliminated. A third means provides the sense amplifier circuit 502 with the task N.
By applying 0P (i), the sense amplifier circuit 502 is brought into a non-operating state. By doing so, it is possible to eliminate the current consumed in the sense amplifier circuit during reading. Although not shown, other means other than the above include:
There is also a method similar to the first method in which a special word line with a small amount of current flowing through the memory cell is selected. By using at least one of the above methods that is suitable for the memory device used, task NOP
It is possible to reduce the read current of the microprogram storage memory at the time. [Effects of the Invention] According to the present invention, in a microcomputer capable of sequentially executing multiple tasks in parallel in a time-sharing manner, a task NOP period in which no task is executed can be set for an arbitrary period at an arbitrary time. Since it can be set, it has the following effects. Current consumption is reduced during the task NOP period. Therefore, the period for executing the task T exc and the task NO.
It becomes possible to control the current consumption of the microcomputer in proportion to the ratio Texc/Tnop of the period Tnop of P. Further, by providing a task NOP, the task execution order and task execution speed can be arbitrarily set to the performance required by the user. Furthermore, in controlling the execution pipeline, the pipeline initialization and -time stop functions can be realized by processing only the upstream stages of the pipeline. That is, the above initialization and -time stop functions can be realized simply by forcibly setting the output signal of the task execution order output circuit to task NOP. Therefore, there is no need for a circuit that delays and supplies the control information for the initialization and -time stop to each pipeline.

[Brief explanation of drawings]

Figure 1 is a block diagram of a microcomputer that can execute multiple tasks sequentially and in parallel in a time-sharing manner, Figure 2 is a block diagram showing details of the register file for address management, and Figure 3 is a block diagram showing details of the register file for address management.
4 is a diagram showing timing related to pipeline control, FIG. 4 is a diagram showing an example of a task execution sequence, and FIG. 5 is a diagram showing means for reducing read current of a memory for storing a microprogram. Explanation of symbols 101... Execution task control memory, 102... Execution task read register, 103... Task NOP
Judgment circuit, 104... Register file for address management, 105... Memory for storing microprogram, 1
06...Microprogram read register, 10
7... Instruction decoder, 108... Arithmetic execution unit, 10
9...Next address generation section. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A first functional circuit that sets a task execution order for executing a plurality of tasks, and a second functional circuit that executes the tasks, the first functional circuit , wherein a specific instruction to the effect that no task is executed can be set, and when the specific instruction is set, it has a function of stopping the functional operation of at least a part of the second functional circuit for a predetermined period of time. A microcomputer featuring: 2. The microcomputer according to claim 1, wherein the specific instruction is a task NOP instruction. 3. The second functional circuit has a memory device that stores a program for executing a task, and a third functional circuit that executes the program, and when the task NOP instruction is set, the 3. The microcomputer according to claim 2, wherein a read operation of the memory device is stopped for a predetermined period. 4. When the task NOP instruction is set, the device has means for fixing the output of the memory device to a value that disables the functional operation of the third functional circuit, regardless of the read data of the memory device. 4. The microcomputer according to claim 3, characterized in that: 5. When initializing the microcomputer, the first
4. The microcomputer according to claim 3, further comprising means for fixing the output of the functional circuit to the task NOP instruction regardless of the setting of the task execution order of the first functional circuit. 6. At any time during the normal operation of the microcomputer, the output of the first functional circuit is sent to the task N regardless of the setting of the task execution order of the first functional circuit.
4. The microcomputer according to claim 3, further comprising means for fixing to an OP instruction. 7. The output data of the first functional circuit includes a code for identifying a task NOP in a bit field for identifying each task. microcomputer.