JPH03261178A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH03261178A
JPH03261178A JP5968090A JP5968090A JPH03261178A JP H03261178 A JPH03261178 A JP H03261178A JP 5968090 A JP5968090 A JP 5968090A JP 5968090 A JP5968090 A JP 5968090A JP H03261178 A JPH03261178 A JP H03261178A
Authority
JP
Japan
Prior art keywords
region
channel region
point metal
transistor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5968090A
Other languages
Japanese (ja)
Inventor
Takeshi Yamano
剛 山野
Yasuo Yamaguchi
泰男 山口
Natsuo Ajika
夏夫 味香
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5968090A priority Critical patent/JPH03261178A/en
Publication of JPH03261178A publication Critical patent/JPH03261178A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent charge storage in a channel region and to prevent a kink effect by discharging charge generated at the channel region as a current to a source region by a high melting point metal film formed on an insulating film under the channel region and the source region. CONSTITUTION:A high melting point metal film 12 is formed on an insulating film 2 under a channel region 6 and a source region 5 of a MOS transistor. When biases are respectively applied to drain, source electrodes 4, 5 and the electrode of a gate 8 to operate the transistor, charge is generated at the region 6 due to an impact ionization, etc., and discharged to the region 5 through the film 12. Thus, charge storage at the region 6 can be prevented, and deterioration of the characteristics of the transistor due to a kink effect can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は、半導体装置およびその製造方法に関し、特
に半導体基板上に絶縁膜、半導体層を形成して作成する
SOIデバイスとその製法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to an SOI device created by forming an insulating film and a semiconductor layer on a semiconductor substrate and a method for manufacturing the same. be.

〔従来の技術] 第2図(a)、 (b)、 (C)に従来のこの種のS
olデバイスの形成過程の断面図を示す。図において、
1は半導体基板、2は絶縁酸化膜、3は半導体層、4は
ドレイン領域、5はソース領域、6はチャネル領域、7
はゲート酸化膜、8はゲート、9は配線分離酸化膜、1
0はドレイン電極、11はソース電極である。
[Prior art] Figures 2 (a), (b), and (C) show a conventional S of this type.
1 shows a cross-sectional view of the formation process of an ol device. In the figure,
1 is a semiconductor substrate, 2 is an insulating oxide film, 3 is a semiconductor layer, 4 is a drain region, 5 is a source region, 6 is a channel region, 7
is a gate oxide film, 8 is a gate, 9 is a wiring isolation oxide film, 1
0 is a drain electrode, and 11 is a source electrode.

まず、第2図(a)のように、半導体基板1上に絶総酸
化膜2、半導体層3を形成する0次に第2図(b)のよ
うに半導体層3をMOS型トランジスタの領域となる部
分を残して除去した後、ゲート酸化1f17、ゲート8
を形成し、さらにドレイン、ソース領域4.5を形成す
る。次に第2図(C)に示すように、配線分離酸化M9
を形成した後、ドレイン。
First, as shown in FIG. 2(a), an absolute oxide film 2 and a semiconductor layer 3 are formed on a semiconductor substrate 1. Next, as shown in FIG. After removing the part leaving behind gate oxidation 1f17, gate 8
, and further, drain and source regions 4.5 are formed. Next, as shown in FIG. 2(C), wiring isolation oxidation M9
After forming, drain.

ソース領域4.5の一部を除去し、ドレイン、ソース電
極10.11を形成する。
A portion of the source region 4.5 is removed to form a drain and source electrode 10.11.

〔発明が解決しようとする課題] 従来のものは、以上のように槽底されているため、各電
極にバイアスを印加して動作させた時、フローティング
状態となっているチャネル領域6にインパクトイオン化
等によって電荷が蓄積され、その影響によってMOS型
トランジスタの特性が劣化し、このキンク効果によりト
ランジスタ動作に悪影響を与えていた。
[Problem to be solved by the invention] In the conventional device, the bottom of the tank is placed as described above, so when a bias is applied to each electrode and the device is operated, impact ionization occurs in the channel region 6 which is in a floating state. Charges are accumulated due to such factors, and the characteristics of the MOS transistor deteriorate due to the influence thereof, and this kink effect adversely affects the operation of the transistor.

本発明は、上記のような問題点を解消するためになされ
たもので、チャネル領域6への電荷蓄積を防止でき、正
常な特性のMOS型トランジスタを得ることのできる半
導体装置およびその製造方法を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and provides a semiconductor device and a method for manufacturing the same that can prevent charge accumulation in the channel region 6 and obtain a MOS transistor with normal characteristics. The purpose is to obtain.

〔課題を解決するための手段] 本発明に係る半導体装置およびその製造方法は、MOS
)ランジスタのチャネル領域およびソース領域の下部の
絶縁酸化膜上に高融点金属膜を形成するようにしたもの
である。
[Means for Solving the Problems] A semiconductor device and a method for manufacturing the same according to the present invention include a MOS
) A refractory metal film is formed on the insulating oxide film below the channel region and source region of the transistor.

〔作用〕[Effect]

本発明においては、チャネル領域に発生した電荷を高融
点金属膜を通してソース領域に電流として流すことによ
り電荷の蓄積を防止できる。
In the present invention, accumulation of charges can be prevented by causing charges generated in the channel region to flow as a current to the source region through the high melting point metal film.

〔実施例〕〔Example〕

以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による半導体装置の形成過程
の断面図を示す。図において、1は半導体基板、2は絶
縁酸化膜、3は半導体層、4はドレイン領域、5はソー
ス領域、6はチャネル領域、7はゲート酸化膜、8はゲ
ート、9は配線分離酸化膜、10はドレイン電極、11
はソース電極・12は高融点金属膜である。
FIG. 1 shows a cross-sectional view of the process of forming a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating oxide film, 3 is a semiconductor layer, 4 is a drain region, 5 is a source region, 6 is a channel region, 7 is a gate oxide film, 8 is a gate, and 9 is a wiring isolation oxide film , 10 is a drain electrode, 11
1 is a source electrode and 12 is a high melting point metal film.

まず、第1図(a)のように半導体基板1上に絶縁酸化
膜2および高融点金属膜12を形成し、MO5型トラン
ジスタのチャネルおよびソースの各領域となる部分にま
たがった部分だけ残して高融点金属膜12を除去する。
First, as shown in FIG. 1(a), an insulating oxide film 2 and a high melting point metal film 12 are formed on a semiconductor substrate 1, leaving only the parts that span the channel and source regions of an MO5 transistor. The high melting point metal film 12 is removed.

次に第1図Cb)のように、絶縁酸化膜2および高融点
金属M12上に半導体層3を形成する。次に第1図(C
)のように、MOS型トランジスタ領域を除いた部分の
半導体層3を除去し、高融点金属膜12の一部に重なる
ようにゲート酸化膜7.ゲート8を形成した後ドレイン
、ソース領域4.5を形成する。さらに第1図(d)の
ように、配線分離酸化膜9を形成し、ドレイン。
Next, as shown in FIG. 1Cb), a semiconductor layer 3 is formed on the insulating oxide film 2 and the high melting point metal M12. Next, Figure 1 (C
), a portion of the semiconductor layer 3 excluding the MOS transistor region is removed, and a gate oxide film 7. After forming the gate 8, drain and source regions 4.5 are formed. Furthermore, as shown in FIG. 1(d), a wiring isolation oxide film 9 is formed to form a drain.

ソース領域の一部を除去し、ドレイン、ソース電極10
.11を形成する。
A part of the source region is removed, and the drain and source electrodes 10 are removed.
.. 11 is formed.

ドレイン、ソース電極4,5とゲート8の電極(図示せ
ず)にそれぞれバイアスを印加してMOS型トランジス
タを動作させると、チャネル領域にインパクトイオン化
等によって電荷が発生するが、高融点金属膜12を介し
て電荷をソース領域5へ放出することにより、チャネル
領域6への電荷蓄積を防止でき、キンク効果によるトラ
ンジスタの特性劣化を防止できる。
When a MOS transistor is operated by applying a bias to each of the drain and source electrodes 4 and 5 and the gate 8 electrode (not shown), charges are generated in the channel region by impact ionization, etc., but the refractory metal film 12 By discharging charges to the source region 5 through the channel region 6, charge accumulation in the channel region 6 can be prevented, and deterioration of characteristics of the transistor due to the kink effect can be prevented.

なお、上記実施例では、絶縁膜およびゲート絶縁膜に酸
化膜を用いた例を述べたが、電気的に絶縁できるもので
あれば何であってもよい。また高融点金属膜12はタン
グステン等、MOS)ランジスタ形成時の熱処理に耐え
うるものであれば何であってもよい。
In the above embodiment, an example was described in which an oxide film was used as the insulating film and the gate insulating film, but any film may be used as long as it can be electrically insulated. Further, the high melting point metal film 12 may be made of any material, such as tungsten, as long as it can withstand heat treatment during formation of a MOS transistor.

〔発明の効果] 以上のように、本発明に係る半導体装置およびその製造
方法によれば、チャネル領域とソース領域下部の絶縁膜
上に形成された高融点金属膜によりチャネル領域に発生
した電荷をソース領域に電流として放出することにより
、チャネル領域への電荷蓄積を防止してキンク効果の発
生を抑え、正常なトランジスタ特性を得られる効果があ
る。
[Effects of the Invention] As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, the charges generated in the channel region can be reduced by the high melting point metal film formed on the insulating film below the channel region and the source region. By discharging current to the source region, charge accumulation in the channel region is prevented, the kink effect is suppressed, and normal transistor characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体装置の形成過程
を示す断面図、第2図は従来のものの形成過程を示す断
面図である。 図において、lは半導体基板、2は絶縁酸化膜、3は半
導体層、4はドレイン領域、5はソース領域、6はチャ
ネル領域、7はゲート酸化膜、8はゲート、9は配線分
離酸化膜、10はドレイン電極、11はソース電極、1
2は高融点金属膜を示す。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a cross-sectional view showing the process of forming a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the process of forming a conventional device. In the figure, l is a semiconductor substrate, 2 is an insulating oxide film, 3 is a semiconductor layer, 4 is a drain region, 5 is a source region, 6 is a channel region, 7 is a gate oxide film, 8 is a gate, and 9 is a wiring isolation oxide film , 10 is a drain electrode, 11 is a source electrode, 1
2 indicates a high melting point metal film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜、半導体層を形成し、半導
体層にMOS型トランジスタを形成したSOIMOS型
トランジスタにおいて、 SOIMOS型トランジスタのゲート電極下部のチャネ
ル領域とソース領域下部の絶縁膜上に形成された高融点
金属膜を備え、 チャネル領域に発生、蓄積した電荷をソース領域に電流
として流し、チャネル領域への電荷蓄積を防止すること
を特徴とする半導体装置。
(1) In a SOIMOS transistor in which an insulating film and a semiconductor layer are formed on a semiconductor substrate, and a MOS transistor is formed in the semiconductor layer, a MOS transistor is formed on the channel region under the gate electrode and the insulating film under the source region of the SOIMOS transistor. What is claimed is: 1. A semiconductor device comprising: a high-melting-point metal film, which causes charges generated and accumulated in a channel region to flow as a current to a source region, thereby preventing charge accumulation in the channel region.
(2)半導体基板上に絶縁膜を形成する工程と、この絶
縁膜上のMOS型トランジスタのチャネルおよびソース
の各領域となるべき部分にまたがって高融点金属膜を形
成する工程と、 上記絶縁膜および高融点金属膜上のMOS型トランジス
タとなるべき部分に半導体層を形成する工程と、 この半導体層上に上記高融点金属膜の一部を覆うように
ゲート電極を形成する工程と、 上記半導体層にドレイン、ソース領域を形成する工程と
を備えたことを特徴とする半導体装置の製造方法。
(2) a step of forming an insulating film on the semiconductor substrate; a step of forming a high melting point metal film over the portions of the insulating film that are to become the channel and source regions of the MOS transistor; and the insulating film and a step of forming a semiconductor layer on a portion of the high melting point metal film that is to become a MOS type transistor; a step of forming a gate electrode on the semiconductor layer so as to cover a part of the high melting point metal film; 1. A method of manufacturing a semiconductor device, comprising the step of forming drain and source regions in a layer.
JP5968090A 1990-03-10 1990-03-10 Semiconductor device and manufacture thereof Pending JPH03261178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5968090A JPH03261178A (en) 1990-03-10 1990-03-10 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5968090A JPH03261178A (en) 1990-03-10 1990-03-10 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH03261178A true JPH03261178A (en) 1991-11-21

Family

ID=13120161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5968090A Pending JPH03261178A (en) 1990-03-10 1990-03-10 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH03261178A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645603A (en) * 1992-07-23 1994-02-18 Nec Corp MOS type thin film transistor
JPH07193248A (en) * 1993-12-27 1995-07-28 Nec Corp Field-effect type transistor and its manufacture
JP2007287732A (en) * 2006-04-12 2007-11-01 Mitsubishi Electric Corp THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645603A (en) * 1992-07-23 1994-02-18 Nec Corp MOS type thin film transistor
JPH07193248A (en) * 1993-12-27 1995-07-28 Nec Corp Field-effect type transistor and its manufacture
JP2007287732A (en) * 2006-04-12 2007-11-01 Mitsubishi Electric Corp THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

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