JPH0326476Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multifunctional liquid crystal digital timepiece that allows switching between a basic timepiece display and several other display modes.

[Prior art] For example, this type of liquid crystal digital watch uses a multi-function watch integrated circuit (hereinafter simply referred to as a watch IC) that uses a one-chip microcomputer.
There is a clock IC in which the display mode of the liquid crystal display can be selectively switched by operating a display mode selection switch connected to the display mode selection input terminal of the watch IC. In this case, for the watch
There are two types of IC display mode switching methods: multiple input (parallel input) type and single input (series input) type, but multiple input type requires display mode selection switches corresponding to the number of inputs. Therefore, these switches are not preferred from the viewpoint of increasing the installation space and complicating the operation. In this respect, the single-input type is advantageous in terms of installation space and operability of the switch.

FIG. 1A is a schematic configuration diagram of a liquid crystal digital watch using a single-input type watch IC, and FIG. 1B is a waveform diagram of each part.

In the figure, 1 is a commonly known watch IC using a 1-chip microcomputer, such as MSM58421-11GS (product name: Oki Electric Industry Co., Ltd.).
is used. Oscillation input terminals 2a and 2b of this watch IC 1 include a crystal oscillator 3 and a capacitor 4.
An oscillation circuit 6 consisting of and 5 is connected. In addition, the display mode selection input terminal 2c of the clock IC1
The display mode selection switch 7 is connected to the day of the week output terminal 2d and the segment output terminal 2.
e, common terminal 2f and mark output terminal 2g
1, 2g2, and 2g3 are connected to respective terminals of a liquid crystal display 8, and an example of the display pattern of the liquid crystal display 8 is shown in FIG. This display pattern consists of 4-digit 7-segment elements S1 to S4, a colon element Co, and 7 day-of-week display elements D1 to D7.
and three mark display elements M1 to M3. Note that the GND terminal 2h of the watch IC 1 is connected to the ground (GND) level, and its V _DD terminal 2i
is connected to the V _DD level of the power supply. In addition, 7
R is a protective resistance.

In such liquid crystal digital watches,
As shown in Fig. 3, the display mode of IC1 is assumed to be switched in the order of basic clock display CL, calendar display DA, stopwatch display ST, and alarm clock display AL. For example, basic clock display
If the display mode selection switch 7 is turned on when the display mode is in CL, the display mode changes to basic clock display CL.
The calendar display can be switched from DA to calendar display. Also,
Furthermore, by turning on the display mode selection switch 7, the calendar display DA can be switched to the stopwatch display ST. Thereafter, by similarly turning on the display mode selection switch 7, the display mode can be switched in series as shown in FIG.

Here, the relationship between the switching operation and the signal output from the mark output terminal will be explained in detail using FIG. 1B.

As is well known, in a liquid crystal display, a common electrode made of a transparent conductive film is formed on the entire back glass.
Display electrodes made of the same transparent conductive film are formed on the front glass provided opposite to this, and liquid crystal is filled between the two glasses. Then, when a voltage is applied between the common electrode and the display electrode, the pattern of the display electrode is displayed. If this applied voltage is direct current, the liquid crystal will electrolyze, so
To prevent this, an alternating voltage is usually applied. In this example, the polarity of the voltage applied between both electrodes is switched at a frequency of 32 Hz. An alternating voltage with the same waveform (rectangular wave with a duty ratio of 50%) is applied to the common electrode and each display electrode, but the display electrode is different from the common electrode.
A signal with an opposite phase that is 180 degrees out of phase is supplied, and a signal that is in phase with the common electrode is supplied to the electrodes that do not display. Between the display electrode and the common electrode,
A voltage is applied due to the phase shift and a display is made, but since signals of the same phase are supplied between the non-display electrode and the common electrode, no potential difference is generated and no display is made.

The signal a in Figure 1B is a reference signal for timing the input and output of each signal, and the common signal e output from the common terminal 2f and supplied to the common electrode has the same waveform as this reference signal a. It's becoming a signal.

At time t1, the display mode is basic clock display CL.
The calendar signal b outputted from the mark output terminal 2g1 and supplied to the electrode of the mark display element M1 has a signal waveform having the same phase as the common signal, so that the mark display element M1 is not displayed. Similarly, the stopwatch signal c is output from the mark output terminal 2g2 and supplied to the electrode of the mark display element M2, and the mark output terminal 2g3
The alarm signal d outputted from the mark display element M3 and supplied to the electrode of the mark display element M3 also has a signal waveform having the same phase as the common signal, so that the mark display elements M2 and M3 are not displayed.

Then, when the switch 7 is pressed to turn on at time t2, the display mode selection input terminal 2c remains at the "L" level (hereinafter referred to as "L") as shown in f for a short time while the switch is pressed. become.
Note that the input terminal 2c is always pulled up to the "H" level (hereinafter referred to as "H").
When the input signal from the input terminal 2c is "L" and the reference signal is "L", the watch IC 1, strictly speaking, detects t3 after a certain period of time after the reference signal becomes "L".
At the time point, it is detected that the mode switching signal is input, and at the next rising time point t4 of the reference signal a,
Switch the display mode from basic clock display CL to calendar display DA.

At time t4 when the calendar display becomes DA, the calendar signal b becomes a signal with an opposite phase that is 180 degrees out of phase with the common signal e. As a result, a voltage is applied between the common electrode and the electrode of the mark display element M1, and the mark display element M1 is displayed to indicate that it is in the calendar display mode.

Next, when the display mode selection switch 7 is pressed again at time t5, a switching input is detected at time t6 and the display mode is switched to stop watch display ST from time t7. As a result, the calendar signal b becomes in phase with the common signal e, and the mark display element M1 disappears.Instead, the stopwatch signal c becomes in phase with the common signal, and the mark display element M2 is displayed.

Next, when the display mode selection switch 7 is pressed again at time t8, a switching input is detected at time t9, and the display mode is switched to alarm clock display AL from time t10. As a result, the stopwatch signal c becomes in phase with the common signal e, and the mark display element M2 disappears. Instead, the alarm signal d becomes in phase with the common signal, and the mark display element M3 is displayed.

Furthermore, when display mode selection switch 7 is pressed again, the display mode returns to basic clock display CL, and t
The state will be the same as at point 1.

[The problem that the idea attempts to solve]

However, when such a single-input type clock IC is used, the display mode functions are fixed, so conventionally, the functions of the stopwatch display and alarm clock display, for example, are unnecessary for the user. It was difficult to obtain a product with only certain functions.

[Means to solve the problem]

This invention was developed in consideration of these points, and its purpose is to provide a single-input type multi-functional watch.
The present invention provides a liquid crystal digital clock that is equipped with only the necessary functions by omitting unnecessary functions when using an IC.

In order to achieve these objectives, this invention
A logic circuit is provided that inputs the common signal sent from each output terminal of the watch integrated circuit and the mark signal whose display is to be skipped among multiple mark signals, and outputs a signal at the same level as the input signal. The output from the circuit is input to the display mode selection input terminal.

[Effect]

In the present invention, with this configuration, unnecessary display modes can be skipped by one operation of the display mode selection switch.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a schematic diagram of a liquid crystal digital watch showing an embodiment of the present invention. The difference from the conventional Fig. 1A is that the common signal is output to the common terminal 2f and the mark output terminal 2 for stopwatch display.
A three-input NOR gate 9 is provided to input signals outputted to the mark output terminal 2g2 and the mark output terminal 2g3 for displaying an alarm clock. Then, the output of this Noah gate 9 is the clock IC 1
The display mode selection terminal 2c is configured to input the input signal to the display mode selection terminal 2c.

The liquid crystal display 8 uses the display pattern shown in FIG. 2 except for the mark display elements M2 and M3 for stopwatch display and alarm clock display.

Next, the operation of the configuration of this embodiment will be explained with reference to FIG. Assume that the liquid crystal display 8 is in a calendar display mode at time t1 in FIG. At this time, as explained in FIG. 1, the calendar signal output from the mark output terminal 2g1 is in opposite phase to the common signal, and the mark display element M1
is displayed. Here, in FIG. 5, a
is the reference signal, b is the stopwatch signal output from the mark output terminal 2g2, c is the alarm signal output from the mark output terminal 2g3, d is the common signal output from the common terminal 2f, e is the NOR signal output from the NOR gate 9. These are the respective waveforms of the output signals.

In this state, the common signal d, stopwatch signal b, and alarm signal c are all in phase, so the NOR output signal e becomes a signal with the opposite phase to the common signal and is input to the display mode selection input terminal 2c. Since the NOR output signal and the reference signal also have opposite phases, when the NOR output signal is "L", that is, when the level of the input terminal 2C is "L", the reference signal becomes "H", and no switching input is detected. Therefore, the calendar display continues.

Here, when the switch 7 is pressed and turned on between t1 and t2, a switching input is detected when the reference signal a is "L" as explained in FIG.
From the point in time, the stopwatch signal b becomes in opposite phase to the common signal d. However, this stopwatch signal is not input to the liquid crystal display 8 but is input to the NOR gate 9. Therefore, the NOR output signal e holds "L", and at t20 when the reference signal is "L"
A switching input is detected at time t3, and from time t3 onwards, the stopwatch signal becomes in phase with the common signal, and instead, the alarm signal c becomes in phase with the common signal. As a result, t3 when the reference signal is “L”
The switching input is detected at time t4, and the alarm signal becomes in phase with the common signal from time t4. At this time, the display mode is simultaneously switched to the basic clock display. When switch 7 is pressed in this state, the display mode changes to calendar display, and t1 in Figure 5 is displayed.
Return to state. If the switch 7 is pressed here, the above operation is repeated. In this example, since the frequency of the reference signal is 32 Hz, one cycle thereof is approximately 31 milliseconds, and the operation of skipping between the two display modes takes only 62 milliseconds.

FIG. 7 is a schematic configuration diagram of a liquid crystal digital timepiece showing another embodiment of the present invention, and shows a case where a commonly known automatic reset circuit is built into the timepiece IC 1. Here, as shown in FIG. 8, for example, the clock IC 1 operates at a preset return time from the time when an automatic return switch (not shown) is operated when the display mode is switched from the basic clock display CL to the calendar display DA. After the calendar display DA
It has a function of automatically returning to the basic clock display CL from CL, and in the embodiment shown in FIG. An inverter 13 is combined with a two-input NOR gate 12 that receives the output and common signals and detects their phase difference, and sends the output of the inverter 13 to the display mode selection input terminal 2c via the display mode selection switch 7. As a result, the basic clock display CL and the calendar clock display DA, which are necessary display functions, are switched and displayed.

The operation of such a configuration will be explained with reference to FIGS. 9 and 10. When the basic clock display is on, the mark output terminal 2g1 and common terminal 2f for the calendar display of the clock IC 1 send out mark display outputs and common signals in the same phase, as shown in FIG. 9a and b, respectively. These mark display outputs and common signals are connected to Noah gate 1.
given to 2. Therefore, the NOR gate 12 obtains an output with a waveform shown in FIG. 9c, and the inverter 13 sends out an output with a waveform in phase with the common signal as shown in FIG. 9d. Therefore, if the display mode selection switch 7 is turned on at this time, the output of the waveform shown in FIG.
IC1 enters the receiving state at the "L" level of its output and operates to switch from the basic clock display CL to the calendar display DA (see FIG. 8). and,
During this calendar display, reverse phase mark display outputs and common signals shown in FIG. Then, this Noah Gate 1
2 sends out the "L" level output shown in FIG. 10c, this output is inverted by the inverter 13, and the inverter 13 sends out the "H" level output shown in FIG. 10d. In this case, the ON operation of the display mode selection switch 7 is unrelated. As a result, the switching from the calendar display to the basic clock display is automatically restored by the function of the automatic return circuit built into the clock IC1, and as shown in Figure 11, only the basic clock display CL and calendar display DA are required. It can be switched as a display function.

Although the above-mentioned embodiment shows a case where the stopwatch display and alarm clock display are skipped as unnecessary display functions, the present invention is not limited to this, and can be applied to a single-pack type clock IC.
, any display function other than the basic clock display can be skipped, and the NOR gate that detects the phase difference between the display outputs can also be used in other logic circuits depending on the input acceptance state of the display mode selection input terminal of the clock IC. Needless to say, it can be replaced with .

[Effect of idea]

As explained above, according to the present invention, a simple logic circuit can be added without making any changes to the multi-function clock IC that serially switches between the basic clock display and several other display modes. A liquid crystal digital clock equipped with only necessary display functions can be obtained.

[Brief explanation of the drawing]

Figure 1A is a schematic configuration diagram of a conventional liquid crystal digital watch, Figure 1B is a waveform diagram of the signals in each part, Figure 2 is a diagram showing the display pattern of the liquid crystal display, and Figure 3 is Fig. 1 is an explanatory diagram showing the display mode switching operation, Fig. 4 is a schematic configuration diagram of a liquid crystal digital watch showing an embodiment of the present invention, and Fig. 5 is a waveform of the main part used to explain the operation of Fig. 4. 6 is an explanatory diagram showing the switching operation of the display mode shown in FIG. 4, FIG. 7 is a schematic configuration diagram of a liquid crystal digital watch showing another embodiment of the present invention, and FIG. 8 is an explanatory diagram showing the switching operation of the display mode shown in FIG. Figures 9 and 10 are waveform diagrams of the main parts used to explain the operation in Figure 7, and Figure 11 shows the display mode switching operation in Figure 7. FIG. 1...Multi-functional watch integrated circuit (watch IC), 2
c... Display mode selection input terminal, 7... Display mode selection switch, 8... Liquid crystal display, 9... Noah gate, 12... Noah gate, 13... Inverter.

Claims (1)

[Scope of utility model registration request] A segment output terminal that outputs signals for basic clock display, a common output terminal that outputs common signals, multiple mark output terminals that output multiple mark signals, and a display mode selection input terminal that inputs signals for changing the display. and a multi-function watch integrated circuit that serially switches between a basic watch display and several other display modes, and a display mode selection switch connected to the display mode selection input terminal of the watch integrated circuit. In a liquid crystal digital timepiece in which an input signal of a predetermined level is inputted by operation and a liquid crystal display is driven by a display output sent from the timepiece integrated circuit in response to the input signal, each output of the timepiece integrated circuit is provided. A logic circuit is provided which inputs a common signal sent from a terminal and a mark signal whose display is to be skipped among a plurality of mark signals, and outputs a signal at the same level as the input signal, and the output from this logic circuit is 1. A liquid crystal digital watch, characterized in that unnecessary display modes can be skipped by operating one of the display mode selection switches by inputting information to a display mode selection input terminal.