JPH03265231A - Repeating installation - Google Patents

Abstract

PURPOSE:To prevent the accumulation of a code error in a frame synchronizing signal and to keep the frame synchronization accurately by multiplexing newly a frame synchronizing signal without any code error at every repeating installation at all times and sending the result to the next low-order repeating installation. CONSTITUTION:An input signal 2 from a decoder 104 is inputted to a frame synchronization circuit 102A and a multiplexer circuit 101. The frame synchronization circuit 102A monitors a frame synchronizing signal and a frame synchronization generating circuit 103 receives a control signal 4 to send a frame synchronization pattern signal 3 without any error to the multiplexer circuit 101. The multiplexer circuit 101 multiplexes the frame synchronization pattern signal 3 without error of time slot for radio circuit included in the input signal 2 and sends the result to a modulator 105. When any code error takes place in the frame synchronizing signal multiplexed on the input signal 2, the code error is not accumulated by the frame synchronization pattern generating circuit 103 and the multiplexer circuit 101 and the frame synchronization is kept accurately.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a relay device, and particularly to a relay device that uses one wireless relay line when transmitting a digital signal from a wireless terminal device to a wireless relay line of the other party. The present invention relates to a relay device that prevents a frame synchronization signal, which is inserted into a time slot assigned to a wireless line by each of the relay devices constituting the relay device, from deteriorating due to an increase in the number of relays.

[Conventional technology]

In conventional wireless relay lines, additional bits of line quality monitoring signals such as frame synchronization signals and parity check signals are inserted into time slots allocated for the wireless line in the wireless terminal equipment. As shown in FIG. 2, the multi-stage relay device constituting the wireless relay line includes
The frame synchronization circuit 102 demodulates the digital signal from the upper relay device, establishes synchronization using the frame synchronization signal from the above-mentioned time slot, and monitors the line quality using a line quality monitoring signal or the like. Furthermore, a data signal 1 including this demodulated frame synchronization signal and a line quality monitoring signal is
07 is input as is to the modulator 105 and sent as a wireless signal to the next lower relay device.

[Problem to be solved by the invention]

In the conventional relay device described above, the frame synchronization signal added to the input demodulated signal is sent to the lower relay device in the same state as it was input, so the deterioration of line quality in each relay section may cause frame synchronization Sign errors in the signal are added. Therefore, the number of code errors in the frame synchronization signal increases in proportion to the number of relays, and in the worst case, the repeater cannot establish frame synchronization, making it impossible to monitor line quality.

[Means to solve the problem]

The relay device of the present invention includes a frame synchronization circuit that establishes frame synchronization from a frame synchronization signal included in a demodulated signal output from a decoder, and a wireless terminal station that uses a frame synchronization position control signal output from the frame synchronization circuit. a frame synchronization pattern generation circuit that outputs a frame synchronization B-turn signal equivalent to the frame synchronization pattern signal, and a multiplexing circuit that multiplexes the demodulated signal to the frame synchronization signal position of a time slot allocated for a wireless line. and has.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a W4 precept diagram of an embodiment of the present invention. The relay device 106A of the embodiment shown in FIG. 1 includes a decoder 104, an additional bit insertion section 1, and a modulator 105. Here, the additional bit insertion section 1 of this embodiment is composed of a multiplexing circuit 101, a frame synchronization circuit 102, and a frame synchronization pattern generation circuit 103.

Next, the operation of this embodiment will be explained. Input signal 2 output from decoder 104 is input to frame synchronization circuit 102A and multiplexing circuit 101. Frame synchronization circuit 102
A monitors the frame synchronization signal mentioned above and sends a control signal 4 to the frame synchronization pattern generation circuit 103. The frame synchronization pattern generation circuit 103 is a circuit having the same function as the frame synchronization pattern generation circuit provided in the wireless terminal equipment (not shown), and sends an error-free frame synchronization pattern signal 3 to the multiplexing circuit 101. . The multiplexing circuit Lot generates a frame synchronization pattern signal 3 with no error in the wireless line time slot included in the input signal 2.
is multiplexed and sent to modulator 105. When a code error occurs in the frame synchronization signal multiplexed to the input signal 2 in this way, the frame synchronization pattern generation circuit 10
3 and the multiplexing circuit 101, an error-free frame synchronization signal is transmitted to the lower relay device.
A code error in the frame synchronization signal that occurs in the third relay section does not affect the frame synchronization operations of the third and subsequent relay devices. Note that the same holds true for the n-th relay device.

〔Effect of the invention〕

As explained above, the present invention constantly multiplexes a frame synchronization signal without code errors for each relay device and sends it to the next lower relay device. is no longer added for each relay, which has the effect of maintaining accurate two-rem synchronization.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the components of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional relay device. 1... Additional bit insertion section, 2... Input signal, 3...
・Frame synchronization pattern signal, 4...control signal, ↓0
DESCRIPTION OF SYMBOLS 1... Multiplexing circuit, 102A, 102... Frame synchronization circuit, 103... Frame synchronization pattern generation circuit, 104... Composite device, 105... Modulator, 106A
, 106... Relay device.

Claims (1)

[Claims] a frame synchronization circuit that establishes frame synchronization from a frame synchronization signal included in the demodulated signal output from the decoder;
a frame synchronization pattern generation circuit that outputs an equivalent frame synchronization pattern signal of a wireless terminal device based on a frame synchronization position control signal output from the frame synchronization circuit;
A relay device comprising: a multiplexing circuit that multiplexes the demodulated signal with the frame synchronization pattern signal at a position of a frame synchronization signal of a time slot allocated for a wireless channel.