JPH03266049A - Extension memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an additional memory device installed in an information processing device.

[Prior Art] When adding memory to an information processing device having a central processing unit (CPU), a method is used in which an expansion connector is provided in the main body and the additional memory is installed according to the user's request. Even if similar devices have different interface specifications, expansion memory devices must be prepared for each device.

Especially recently, the speed of CPUs has improved significantly, and although the interface specifications are logically the same for functionally similar devices, there are cases where the timing is different, and as the main devices become faster, the clock frequency increases. Therefore, the method of creating a wait signal by counting the clock frequency does not have enough access time, so the additional memory may not work. Conventionally, the shortage of weights due to faster clock signals has been dealt with by changing the control circuit, such as by using a dip switch to change the setting softness.

FIG. 3 is an example of a circuit according to the prior art. In devices using memory that requires 3 clocks for a fast clock and 2 clocks for a slow clock to access the memory,
5 indicating the start of access made by the memory control circuit 301
This circuit counts the TART signal 307 using flip-flops (hereinafter abbreviated as FF) 302 and 303, switches the output of 302 or 303 using the switch 305 and selector 304, and outputs the READY signal 310 to the main unit, and the circuit outputs the READY signal 310 to the main unit. In order to use the memory, it was necessary to access the memory at a fixed speed by turning off the switch 305 when using a fast clock and turning on the switch 305 when using a slow clock.

FIG. 4 is a timing diagram for the circuit in FIG. 3. In the case of the fast clock in FIG. 3(a), the switch 305 is turned OFF, so the FF is
The signal 309 delayed by FF 302 and FF 303 becomes the READY signal 310, and it takes three cycles to access, but the third
In the case of the slow clock shown in Figure (b), switch 305 is turned off.
By setting N, 5 TARTI word 307 to FF
The signal 308 delayed at 302 becomes the READY signal 310, changing the access to two cycles.

[Problem B to be solved by the invention] In the conventional technology, considering that an additional memory device is installed in two or more types of main unit with different speeds, the time required for memory access is determined by the type of memory, so It is impossible to set it by itself, and it is determined by the combination of the additional memory device and the main device. The operating speed at that time is determined by factors such as the CPU clock, so depending on the machine itself, if you want to install additional memory on a completely different machine body, you will need to set the weight number to match the machine body using a dip switch etc. There was a problem.

An object of the present invention is to maintain a constant access speed without changing the settings of the main body, and to use an additional memory device in an optimal state.

[Means for Solving the Problems] The present invention provides an information storage system having a main body including a central processing unit (CPU) and a bus line synchronized with a clock signal of the CPU, and an additional memory section installed outside the main body. The processing device is characterized by comprising a control mechanism for setting the access time to a fixed amount when the CPU accesses the additional memory.

[Example] An embodiment of the additional memory device of the present invention will be described below.

FIG. 1 is an example of a circuit according to the present invention.

A memory control circuit 101 is a circuit similar to a conventional circuit, and supplies signals necessary for memory access, and also generates an S'TART signal 105 indicating the start of access. The delay line 102 is used to secure the time necessary for access, and the delay time is determined by the type of memory used in the expanded memory device. The FF 103 is provided to synchronize the output 106 of the delay line 102 with the clock 104, and outputs a synchronized READY signal 107 to the main body. This delay line 102 can achieve its purpose if it operates in the same way, and may be a timer circuit, for example.

FIG. 2 is a timing chart of the circuit shown in FIG.
The AS and CAS signals are general RAM control signals for reference, and the opening and opening of the potential "LOW" of the RAS signal corresponds to the access time. In the case of the fast clock shown in FIG. 2(a), DEL delayed from the 5TART signal 105.
READ the AY signal 106 in synchronization with CLK]04
It takes three cycles to access to generate the Y signal 107, but in the case of the slow clock shown in FIG. The number of cycles until output decreases, and access ends in two cycles, indicating that the number of access cycles changes without changing the settings.

[Effects of the Invention] According to the present invention, one type of additional memory device can be connected to two different speeds.
It can be installed on various types of main bodies without changing settings, and can be used at fixed access speeds.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the present invention, Fig. 2 is a timing diagram of the circuit of Fig. 1, and (a)
is a fast clock, and (b) is a slow clock. FIG. 3 is a conventional circuit diagram, and FIG. 4 is a timing diagram of the conventional circuit, where (a) shows a fast clock and (b) shows a slow clock. 101.301...Memory control circuit 102φφ...Delay line 103.302.303...Flip-flop 305.
...Switch 304...Selector or higher

Claims (1)

[Claims] In an information processing device having a main body including a central processing unit (CPU) and a bus line synchronized with a clock signal of the CPU, and an additional memory section installed outside the main body, the CPU accesses the additional memory section. and when,
An expansion memory device characterized by comprising a control mechanism for setting the access time to a fixed amount.