JPH03268518A - Interleaving synchronizing system - Google Patents

Abstract

PURPOSE:To set up interleaving synchronism by error correcting syndrome without adding a synchronizing pulse by periodically changing the syndrome for turning all codes to '0' after coding a signal on a transmitting side, and allowing the period to coincide with an interleaving frame. CONSTITUTION:A coding signal inverts the 1st bits in plural blocks, i.e., the 1st block to the (m-1)th block, out of m(=5) blocks in one interleaving frame and inverts the 2nd bit in the m-th block. In the transmitting side, an error correcting coder 10 corrects and codes an input signal, an inversion circuit 12 executes said bit inversion based upon an interleaving synchronizing position pulse outputted from the coder 10 and an interleaver 14 executes interleaving based upon an interleaving synchronizing position pulse outputted from the inversion circuit 12 to transmit an output. On the receiving side, a frame synchronizing circuit 26 sets up synchronism between interleaving and error correction, a deinterleaver executes deinterleaving, an inversion circuit 22 returns bits inverted on the transmitting side to normal bits, and an error correcting demodulator 24 executes error correcting demodulation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Use) The present invention is used in digital communications. In particular, the present invention relates to synchronization of an interleaver system that randomizes burst errors and corrects the errors using an error correction code.

(Prior Art) Conventionally, various error control methods have been developed, centering on error correction and detection codes. In particular, interleaving is effective as a method for improving the performance of random error correction codes by randomizing burst errors. FIG. 4 shows the bit configuration of conventional interleaving. When interleaving and block error correction codes are used together, it is necessary to establish word synchronization of block codes and synchronization of interleaving, respectively. In contrast, there is a conventional method in which word synchronization of block error correction codes is established when interleave synchronization is established by setting the interleave size to an integral multiple of the error correction block length. According to this method, the number of pulses for frame synchronization, the synchronization pull-in time, and the number of circuits for frame synchronization can be reduced compared to the case where synchronization is established separately.

Methods for establishing word synchronization of block codes include a method of inserting a synchronization pulse and a method of calculating syndromes. When inserting a synchronizing pulse, there is a disadvantage that the transmission capacity decreases accordingly. An example of a method based on syndrome calculation is JP-A-63-226147.

Japanese Patent Application Laid-Open No. 63-226147 relates to a block synchronization method in which signals coded using error correction codes of multiple (n) sequences with established clock synchronization are transmitted in parallel, and block synchronization is established on the receiving side. Block synchronization is established by i) shifting the initial phase of each block and calculating the syndrome from the same phase for each series, and (ii) calculating the syndrome from different phases for multiple data sequences having the same initial block phase. It is something to do.

When using block codes and interleaving together, it is necessary to make the interleave size longer than the code length of the block code, and in that case, interleave synchronization cannot be established only by using synchronization of the block codes.

(Problem to be Solved by the Invention) However, in interleaving, there has been no conventional method for establishing synchronization by calculating syndromes, and synchronization pulses have been inserted. Therefore, when block codes and interleaving are used together, there is a drawback that the transmission capacity due to synchronization pulses is reduced. Therefore, the present invention aims to improve the above-mentioned drawbacks and provides an interleave synchronization method that does not reduce transmission capacity.

(Means for Solving the Problems) A feature of the present invention for achieving the above object is to extract one bit from each clock of a block error correction code of code length n over m blocks, and extract an interleaved size rabbit (j= In an interleave synchronization method that configures and transmits and receives an interleave frame consisting of nXm), on the transmitting side, at least one
at least one bit (1≦k≦n) of j≦m)
The syndrome is given periodicity by inverting it after error correction coding, and is transmitted without a synchronization code, and on the receiving side, the received signal is processed using a data sequence extracted every d bits with an interleaving depth of d. to establish the word synchronization phase of the error correction code in the word synchronization circuit,
Interleave synchronization, in which a syndrome is calculated using the word synchronization phase of data of a data series extracted from the received signal every d bits, and a phase of interleave synchronization is established from the periodicity of the syndrome without using a synchronization code. It's in the method.

(Operation) The present invention periodically changes the syndrome that becomes O after encoding on the transmitting side, and by matching the period with the interleaf frame, interleaving can be performed by the error correction syndrome without adding a synchronization pulse. Establish synchronization.

(Example) FIG. 1 shows an example of the present invention. In Figure 1, 10 is an encoder for error correction, 12 is a code inversion circuit, 14 is an interleaver, 20 is a tinterleaver, and 22 is a code inversion circuit for restoring the code inverted at 12. , 24
is an error correction decoder, and 26 is a frame synchronization circuit. 1
The sign reversal by 2 and 22 is an important feature of the invention. Further, an embodiment of the frame synchronization circuit shown in FIG. 1 is shown in FIG. Figures 3a to 3e show the interleaving structure and the relationship between inversion bits. For example, the encoded signal shown in FIG. The block inverts the second bit. Third
The figure shows this relationship.

On the transmitting side, the error correction encoder performs error correction encoding, and then the inversion circuit inverts the signal as described above based on the error correction synchronization position pulse output from the error correction encoder.

Thereafter, interleaving is performed in the format shown in FIG. 3C based on the interleave synchronization position pulse output from the inverting circuit, and the data is transmitted as shown in FIG. 3D.

On the receiving side, a frame synchronization circuit establishes synchronization between interleaving and error correction, performs deinterleaving, and an inverting circuit restores the bits inverted on the transmitting side to normal.
After that, error correction decoding is performed.

As shown in Fig. 3e, the frame synchronization circuit first consists of 17
Serial-to-parallel conversion to m. This allows each m-series signal to form a block. When the syndrome is calculated for each signal of the m series, the syndrome of the (m-1) series is such that the first bit is inverted at the phase that matches the error correction cycle, so for example, in the case of a BCH code, ao (α: (root of the generator polynomial), and in the other series, the second bit is inverted, so the syndrome is α1. At this point, error correction word synchronization is established. This word synchronization method is similar to the conventional technology (for example, Japanese Patent Laid-Open No. 63-226147). That is, in this case, it is sufficient to calculate the syndrome for each of the five signal sequences by shifting one bit, and to establish word synchronization at the closed point where the syndrome becomes, for example, 0. In this way, syndromes S~S5 are calculated for the five series. When these 31 to S match a predetermined pattern, interleave synchronization is established. In this case, 31 to S5 (α0α0α1α0α0
), interleave frame synchronization is performed at S4.

One embodiment has been described above, but the feature of the present invention is to establish interleave synchronization by giving periodicity to the syndrome, and the bit position to be inverted can be freely selected as long as there is periodicity. Further, the number of bits to be inverted can be freely selected within a range that can be corrected and detected by the error correction circuit. Of course, it is not necessary to invert all blocks. Further, as long as the error correction code is a block code, it can be applied to any code such as BCH or Reed-Solomon. Further, although a plurality of syndrome calculation circuits are provided in the embodiment, it is also possible to sequentially calculate the syndrome of each series using one syndrome calculation circuit used in the error correction decoder. Furthermore, if the interleaving size is an integer m times the error correction code length, m does not need to match the interleaving depth d. Furthermore, in the embodiment, either a synchronization pulse is not inserted in both the error correction and interleaver, or an error correction word synchronization pulse is inserted, and after establishing error correction word synchronization with this synchronization pulse, interleaving frame synchronization is performed. The present invention also includes a method of establishing the syndrome by utilizing the periodicity of the syndrome.

(Effects of the Invention) According to the present invention, synchronization of error correction codes and interleaving can be established without inserting any frame synchronization pulses. Therefore, it is possible to avoid a reduction in transmission capacity or an increase in occupied bandwidth due to synchronization pulses. Note that the present invention does not reduce the error correction effect. This is because the inverted signal remains inverted in the frame synchronization circuit, but after synchronization is established, it is inverted again in the inversion circuit on the receiving side, returns to normal, and is input to the error correction decoder. This is because it is not an error.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the transmitting side and receiving side of the interleave synchronization circuit according to the present invention, FIG. 2 is an embodiment of the frame synchronization circuit, FIG. 3 is an explanatory diagram of the operation of the present invention, and FIG. 4 is the conventional technology. It is an explanatory diagram. 10; error correction encoder, 12; inversion circuit, 14; interleave, 20; deinterleave, 22; inversion circuit, 24; error correction decoder, 26; frame synchronization circuit,

Claims (1)

[Claims] An interleaving method in which one bit is extracted from each block of a block error correction code having a code length n over m blocks to construct an interleave frame having an interleave size j bits (j=n×m) for transmission and reception. In the synchronization method, at the transmitting side, at least one i-th block (1≦i
≦m) by inverting at least one k-th bit (1≦k≦n) after error correction coding to give periodicity to the syndrome, transmitting without synchronization code, and transmitting the received signal on the receiving side. The interleaving depth is d
A word synchronization phase of an error correction code is established in a word synchronization circuit using a data sequence extracted every d bits as a data sequence, and the data of the data sequence extracted every d bits from the received signal is synchronized using the word synchronization phase. An interleave synchronization method characterized in that the phase of interleave synchronization is established from the periodicity of the syndrome without using a code for synchronization.