JPH0326872B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device,
Specifically, functional devices using existing control technology, functional devices designed for the purpose of vector calculations, and data processing devices that include data paths for scalar calculations to achieve that purpose. It is related to.

[Prior art]

The following US patents are representative of existing data processing structures that perform vector data processing.

U.S. Pat. No. 4,128,880 discloses a processor specifically designed for vector processing, but it requires its own programming and relies on a host computer to provide it with vector data for processing. There must be. This US patent also shows other processors that process at extremely high speeds for extremely large programs, offering possibilities beyond the needs of many users.

Another example for processing vector operands is US Pat. No. 4,172,287. A general-purpose data processor originally designed for scalar computations, modified to include an arithmetic and rotation unit designed to process a pair of operands to execute each instruction, Vector instructions can now be identified. Most of the modifications involve handling of memory address operations for vector element access. Vector buffers are added and used only under very limited memory addressing conditions to speed up the overall processing. However, even with this modification, the original arithmetic unit is still used. The latter US patent also requires additional storage due to the microprogramming of vector instructions, with the inherent slowdowns associated with this form of execution control. Furthermore, the interrupt processing power of the basic processor depends on the state of vector processing if the accuracy of error processing is low.

[Problem that the invention seeks to solve]

The problems to be solved by the present invention are as follows.

(1) To provide a general data processing system that has high-speed vector processing capability by simply connecting a vector processing function device to the basic instruction processing/execution device of a central processing unit (CPU).

(2) Basic data and microprogramming control that requires only microprogramming control to provide propulsion signals to vector function devices.
To provide vector processing for processors.

(3) Providing precise interrupt and error information to the appropriate underlying system to correctly handle vector exception conditions.

(4) A functional device for vector processing that includes an addressable vector register and a masking capability that allows flexible processing to be performed only on specific elements in a long chain of elements. to provide.

[Means for Solving the Problems] The above-mentioned problems address the exceptional conditions for parallelizing pipelined arithmetic units, pipelined arithmetic units including addressable vector registers, parallel adders, and multiplication/division units, or The solution is a hard-wired vector processing function unit that includes an error indication wheel and a mask wheel for operand access control. Vector functional units depend entirely on the instruction processing and control processing of the basic processor, the operand fetching and storage capabilities of the basic unit to receive instructions to execute, and the vector elements to be operated on. The vector processing function unit advances vector processing in synchronization with the base system by receiving advance signals from the base system's microprogram control.

The computational pipeline of a vector processing function unit consists of multiple stages, each stage containing logic to indicate an exceptional condition or error. Logic that indicates an exception condition or error prevents erroneous results and provides information about the exception condition or error to the underlying system for correct processing and recovery from the exception condition.

Integrating some elements in the mask register and the vector store of the logical vector function unit provides the flexibility of handling only some elements of a long vector. As a result, once an element is accessed, the processing becomes less troublesome, and the pipeline of the arithmetic unit can be used very effectively.

〔Example〕

FIG. 2 is an overall diagram of a data processing system including the VPU 20, which is the object of the present invention. The remaining parts except VPU20 in Figure 2 are covered by the US patent.
It is a basic data processing system as disclosed in No. 4200927.

Memory device 21 includes processor memory 23 and processor storage control function (PSCF) 24. Memory device 21 is used to store program instructions and data operands, including vectors to be processed by VPU 20. The CPU 22 includes an instruction preprocessing function (IPPF) 25 and an E function unit 26 . Details of these devices can be found in U.S. Patent No.
It is disclosed in No. 4200927. IPPF 25 takes care of fetching and decoding all instructions to be executed by E function 26 and all instructions to be executed by VPU 20. E function 26 executes instructions that process non-vectors and creates a data path 27 between E function 26 and memory device 21 . E function 26 has a microprogram control store for generating instruction execution control signals.

Interconnection between the basic data processing system and the VPU 20 is provided by an interface 28 between the VPU 20 and the E function 26, and an interface 29 between the VPU 20 and the IPPF 25.

FIG. 1 shows various functional units of VPU 20 and CPU 22. Details, including information, will be found in the description of interfaces 28 and 29 shown in FIG.

The interface 29 transfers vector instructions from the I element instruction queue 30 in the IPPE 25 to the vector instruction register 31 and Q instruction buffer 32 of the VPU 20.
Send the OP code.

Interface 29 is also used to transfer address information between vector index register 33 and stride register 34. Strand register 34 contains address information specifying main memory address divisions between ordered vector elements.

Details of the interface 28 between the VPU 20 and the E function 26 of the CPU 22 are shown in FIG. Figure 2
Data transfer between the VPU 20 and the memory device 21 is performed by a data bus 35. Data transfer from the memory device 21 to the VPU 26 in FIG. From the VPU 20 to the memory device 21 in Figure 2
Data transfer to register 38 in VPU20
or from lambda register 39 to bidirectional bus 35
to bus 27 via register 40 in E function 26.

Multiple calculation pipeline processing is performed in the VPU 20, and a large amount of address calculations are performed when processing long vectors. Various error conditions
When an error condition occurs in CPU 22 or VPU 20, it is important to indicate the exact point in the instruction execution order where the error condition occurs.

One error condition that may arise involves the detection of an error in accessing data from memory device 21 to E function 26. Rather than aborting all processing in response to the detection of an error in the E function 26, the access exception condition is received at 41 in the E function 26 and sent via line 42 to the access exception condition mechanism 43 of the VPU 20. sent to. The exception conditions received by 43 are utilized at subsequent times to provide more accurate information as to how much instruction processing has been performed on a long string of vector elements. This will be discussed later.

Other error conditions that may arise relate to the detection of computational errors in VPU 20. In response to an arithmetic error, an exception condition code is generated at 44 and sent via line 45 to a status indicator 46 of CPU 22. Operational exception conditions are expressed in coded form,
It is stored in a status indicator (trigger) 46 for analysis by the CPU 22 and used to determine the corrective action to be taken.

As previously described and shown in FIG. 1, the E function 26 has a microprogram control store 47 as its basic control mechanism. Branch branch or control memory 47
Changes in the order of execution of microinstructions within are signaled by wheel 48 to indicate various branch points. Various signal lines representing branch requests are signaled by service request 49 from VPU 20 and sent to branch point wheel 48 via line 50.

The one last line shown in FIG. 1 (the line that is part of the interface of FIG. 2) is line 51. When a microinstruction is read from control memory 47 and placed into data register 52, the decoder
An execution control signal is given to the E function 26 of the CPU 22.
As part of the present invention, timing control of the operation of VPU 20 is provided by the basic clock cycles of CPU 22. The sequential progression of the various functions of VPU 20 follows line 5 from the decoding of data register 52.
Under the control of the signal above 1. This signal is propulsion 53
It is named. All timing and gate activation in VPU 20 is controlled and synchronized with the microinstruction sequence on line 51,
Responsive to all logic at 0 and a driving pulse on line 54 going to the gate.

Figure 3 shows the VPU signaled on line 50 of Figure 1.
20 state information is shown which is used by branch point processor 48 to control the order of microinstructions from control store 47. Signal lines 55 and 56 represent vector processing related signal lines from IPPF 25 and E function 26 of FIG. Branches in the microinstruction order of control store 47 are:
Occurs in several VPU 20 states to indicate VPU 20 readiness, requirements for operand fetch or store, end of vector instruction, and vector exception condition indications.

FIG. 4 shows various paths of the VPU 20 of the present invention,
Indicates a register, functional device. VPU20 and CPU
Some of the registers and buses involved in the interface between 22 and 22 were previously described in connection with FIG. The bus includes interface lines 29 and 35. The registers are data-in register 37, register 3 labeled stage A and random, respectively.
8 and 39, instruction register 31, instruction buffer 3
2, and an address index register 33.

These registers, other registers not yet described, and the functionality of the arithmetic unit are described below. Figure 4 shows the vector register array 57.
It is shown. This array 57 contains 16 vector registers (VR), each VR containing 128 4
It is made up of bite elements. VRs may be combined (in odd-even pairs) to form double word operands. Addressing of vector register array 57 is associated with a number of address registers (indicated generally at 58 in FIG. 4) described below.

Stage A register 38 and stage B register 59 receive data read from VR 57. Data from register 38 goes either to the vector data path or to E function 26 depending on the instruction. Register 38 can also receive data from a vector mask register (VMR) on line 60. The functions of VMR will be described later. Register 39 is used as a delay register for the flow of operational data as well as a backup register for data being sent from register 38 to E function 26. Data delay is necessary to perform correct VR access.

Registers 61 and 62 receive information from various sources. Its output is sent to pre-shift logic used during exponent matching for floating point operations.
Arithmetic and processing units (ALUs) in registers 63 and 64, respectively, are staging registers containing data to be processed by ALU 65.
Arithmetic/Line Unit (ALU) 65 is a parallel binary adder. ALU output register 66 holds the output of ALU 65 obtained in the previous cycle.
A post normalization wheel 67 is provided for floating point operations. The input of ALU fetch register 68 receives the output of post-normalization wheel 67. register 68
acts as a delay register for data circulating to the ALU 65. Register 68 is register 61,
Together with 63 and 66, it forms a 4-cycle closed circuit. This is used for the vector accumulation instruction described below.

Index register 33 receives the output of register 68 as an input. Index register 33 is used to hold addresses that occur during index type instructions. In certain cases, the address is then IPPF2 as shown in Figure 1.
5 address incrementer.

VR fetch register 69 serves as a stage for data written to VR array 57. The input is from register 37 or from fetch bus 70 which has several sources.

Registers 71 and 72 are a multiplication stage A register and a multiplication stage B register, respectively.
These registers contain data to send to the remainder of the multiplication data path, including the exponent sum logic 37.
Multiplicand A stage register 74 holds the multiplicand for multiplications, the divisor for divisions, and also buffers the dividend during division functions. Multiplier register 7
5 stores a multiplier for multiplication and stores a quotient for division.

The outputs of registers 74 and 75 are sent to multiplication/division device 7
This is the input for 6. A product/quotient register 77 and a post-normalization wheel 7 are connected to the output path of the multiplication/division device 76.
There are 8. The last register in the multiply/divide data path is the multiply fetch register 79, which receives the output of the postnormalization wheel 78 and for all vector divide instructions as part of the divide function and for certain complex vectors. Serves as a delay register for data to be provided to the data path of ALU 65 for instructions.

The aforementioned register 37 serves as a buffer for data coming from register 36 in E function 26 of FIG. The ALU 65 is an arithmetic/cycle unit that performs addition and subtraction on binary short-precision operands and long-precision operands. ALU65 is
AND, OR, and EXOR operations and operations that logically shift the operand by 0, 1, 2, or 3 bits to the left can be performed.

Instruction buffer 32, which receives information from interface 29, holds vector register addresses and vector instruction OP codes used by other decoding circuits in VPU 20 during instruction execution.

In Figure 4, the vector operand data is
It comes from CPU 22 via VR array 5 or data in register 37. Both operands
When arriving from VR array 57, the first vector element travels through the A side of the data path. The second vector element travels through the B side of the data path. All parts of the data path (ALU65
or the multiplier/divider unit 76) steps simultaneously.
Initially, the first element of the A-side vector operand is 1 greater than the first element of the B-side vector operand.
It is read out from the VR array 57 a cycle early. Thus, after two cycles A-side element 1 is in lambda register 39, B-side element 1 is in stage B register 59, and A-side element 2 is in stage A register 38. This initial offset is VR array 5
7 to accommodate a single port array chip. This offset, in conjunction with the circular vector arrangement in the physical array chip described below, ensures that only one read from any array chip occurs during any given cycle. The vector result from VR fetch register 69 is stored in VR array 57 for each machine cycle.

When there is one vector from memory device 21 of FIG. 2 and there is also one vector from VR array 57, the vector from VR array 57 flows through the B side of the data path. The vector coming from E function 26 enters register 37 and then
ALU shift A register 61 or multiplication stage A
Flows through the A side of the data path starting in either register 71. The vector results are written to the destination VR array 57 as specified by the instruction.

When there is one vector from VR array 57 and a scalar operand from E function 26,
The CPU 22 uses a certain signal to use the ALU 65 or multiply
Divide unit 76 sends a scalar operand to either A side of the data path. The scalar operand is
ALU shift A register 61 or multiplication stage A
It is held in one of the registers 71 and supplied to the subsequent wheel. The operands of VR array 57 flow through the B side of the data path. The results are written to destination VR array 57.

When there is one vector from memory device 21 and one scalar element from E function 26, CPU 22 transfers the scalar operand to ALU 65.
or any A of the data path of the multiplication/division device 76
Generates a signal to be sent to the other side. CPU 22 then issues a push signal to step the vector storage operand through the B side of the data path. The results are then written to the destination VR array 57.

elements of a series of vectors from memory device 21
The data transfer path for the vector load instruction when it is to be transferred to the VPU 20 is from the CPU 22 to the register 6, the data bus 35, and the data in register 37. The data is then stored into VR array 57 via VR fetch register 69. Each time an element is written into VR, the vector element address register described below is set to 1.
is incremented. For load instructions that use strands (i.e., memory addresses between successive elements other than 1), the CPU 22 calculates the storage address of the vector element, makes a fetch request to the memory, and processes a maximum of one element per cycle. Transfer data at speed. For vector load instructions that use mask registers, described below, the bit mask is tested to determine whether a particular element is to be loaded into VR 57. For instructions that use an index vector as part of the address calculation, VPU 20 calculates the storage address.
Then that address is sent via interface 29.
Sent to CPU 22 to make a fetch request and transfer the data to VPU 20 via data bus 35.

During a vector store instruction, the VPU 20 stores data
Transfer from VR 57 to CPU 22 via stage A register 38 and bidirectional data bus 35.
If a clock stall condition occurs in CPU 22, one signal becomes active in VPU 20 one cycle later. The data that should have been placed on data bus 35 is held in lambda register 39. When execution resumes, the data in lambda register 39 is placed on data bus 35. In a similar manner to vector load instructions,
Address calculations, vector mask usage, and index vector usage are performed.

FIG. 5 shows forced control of cycling of the VPU 20 by the CPU 22. Elements previously mentioned in CPU 22 include control store 47, control store data register 52, and register 36. The forced control exerted by the CPU 22 is accomplished by detecting a particular micro-sequence of particular micro-instructions in the control storage data register 52 which sets a one-cycle trigger 80 labeled CP Proceed. be done. Signal line 51 is energized to generate a VP propulsion signal 54 at 53, which signal is transmitted to VPU2.
0 to all datapath gates of the interstage datapath. Vector data is not propelled through the data path unless propulsion signal 54 is present. This is mandatory for VPU20
Ensures control and synchronization of the CPU 22. When vector drive signal 54 is not active, each register in the data stream holds its data. When active, data is gated as directed by instructions in VPU 20.

FIG. 5 shows the data valid bits that parallelize the functional data paths in the VPU 20. An initial data valid bit, indicated at 81, is associated with data register 36 of CPU 22 and is set by the microinstruction micro-order to indicate that the contents of register 36 are valid and can be gated to VPU 20. The function of the data validity bit is to ensure the validity of the data being processed at a particular stage. The absence of the data valid bit associated with fetch register 69 prevents updating of VR 57. Depending on the source of the operands, the output of CPU 22 or VR 57 sets the data valid bit for each element to be processed and resets the data valid bit after the last element has been processed.

When data valid bit 82 associated with fetch register 69 allows updating of VR 57, a counter is incremented to indicate the number of vector elements that have been successfully processed. This counter also indicates the completion of processing all elements of the vector. This counter is used in situations where an error has occurred and where it is necessary to indicate the total number of correctly processed elements when processing for a particular vector instruction is resumed. The path of data valid bits through the data path is defined by the control lines depending on the particular vector command being executed.

All elements shown in FIG. 6 have been previously described and have the same reference numerals as before. 6th
The figure shows VPU for two typical vector instructions.
2 shows two configurations of data flow paths within 20. The solid line data path shows the form for executing the VR accumulation instruction, and the dashed line path shows the form for executing VR and main memory multiplication/
2 shows a form for executing an accumulation instruction.

For vector accumulate instructions, the four partial sums are
It is read from VR57 and sent to the A side of the data stream. The partial sum is stored in the stage A register 38, lambda register 39, ALU shift A register 61,
and ALU in register 63. Reading of the B side data stream begins when the first partial sum is reached by register 63 and the valid bit for that stage is turned ON. The data in the data path is read out on the intermediate B side which continues to step.

The element to be accumulated is the stage B register 59.
Upon entry, the first partial sum from the A side of the data stream enters the ALU fetch register 68. At the next propulsion pulse, the contents of the ALU extraction register 68 are transferred to line 8.
3 to the ALU shift A register 61,
Meanwhile, the contents of stage B register 59 are changed to ALU
Transferred to shift B register 65. The propulsion pulse now steps both operands in the data stream, first sending the accumulated result to the ALU output register 6.
6 to ALU fetch register 68 and via line 84 to VR fetch register 69. The VR retrieval register 69 transfers the accumulated result to one of the four partial sum locations of the VR 57.
send it to one. ALU fetch register 68 sends all results back to ALU shift A register 61. This partial sum is then combined with other elements from the B side.
The signal is supplied to the ALU 65 and this operation continues. The result of the accumulate instruction is as follows. That is, every fourth element is added and the result is placed in one of the four partial sum locations of the vector register.

The dashed lines in FIG. 6 indicate an arrangement for multiplication and accumulation using data from main memory. The first drive pulse gates data from storage into data-in register 37 and drives the first element of the VR57 operand into stage B register 59. The second propulsion pulse gates data in register 37 into multiplication stage A register 71 and gates stage B register 59 into multiplication stage B register 72.
and gates the first partial sum into stage A register 38. The gate energized with the second propulsion pulse is used for an additional five cycles.
At this point, five more elements have been read into the data stream of the multiplier/divider unit 76. However, the data in the multiply fetch register 59 has not yet been confirmed to be valid, and a partial sum of 0 is present in the ALU fetch register 68. Data flow towards ALU 65 is blocked from further forwarding until multiply fetch register 79 indicates valid data. When the valid data and its associated valid bits reach the multiply fetch register 79, the next propulsion pulse gates the ALU fetch register 68 to the ALU shift A register 61 and the multiply fetch register 79 to the ALU shift B register 62. do. After four more steps, the accumulated result of the first partial sum and the multiplication result with the significant bit are
ALU fetch register 68 and VR fetch 69 are reached. Writing the result to vector register 57 begins when the first sum of products and partial sums 0 is
This is when the ALU extraction 68 is reached.

7, 8 and 9 illustrate vector register array 57 and vector register array addressing mechanism, indicated schematically at 58 in FIG. Array 57 includes 16 vector registers (VR) of 128 4-byte elements each. They can be assembled (odd and even pairs) to form VR double word operands. The entire array takes the form of a 64 array chip 85. Each chip 85 is 9 bits wide (8 bits + parity bit). array chip 85
Since it is limited to only one read/write per cycle, it is necessary to interleave the VR four ways as shown in FIG. Each column of the array 57 is
It represents one interleave consisting of 16 chips 85 divided into four groups. Each row of array 57 represents four VRs. The relationship of elements 0 to 127 with respect to vector register number 0 (VR0) formed in four columns is shown in FIG.
VR can provide two elements per cycle for vector operations and can receive one element per cycle from vector operations or from CPU 22. 7 shows the data path for reading from the VR register to a stage register such as 38, and FIG. 8 shows reading data into the VR via the VR fetch register 69.

The addressing details of vector register array 57, shown schematically at 58 in FIG. 4, are shown in FIG.
Three vector element address registers VEAR
There are 1, VEAR2 and VEAR3. These registers are indicated generally by the reference numeral 86 in FIG. VEAR2 and EAAR3 typically contain the number of elements of the source vector read from VR during any given cycle. VEAR1 contains the number of elements of the vector written to VR.

VEAR1 is also used as the vector interrupt index (VIX) for most vector instructions that write results to VR. Each VEAR is updated by its own incrementer and loaded from the data in register 37 shown in FIG.

VIX is incremented only when the data valid signal associated with VR fetch register 69 acts to permit writing to VR. Therefore, if an error condition indicates that VR should not be updated, VIX is not stepped and displays the number of elements that have been processed during execution of the particular instruction. This information is available when the instruction is resumed after any fixed routine.

The addressing mechanism also includes three vector address registers (VARs). These registers are indicated generally at 87 in FIG. VAR is
They are marked as VAR1, VAR2, and VAR3. VAR
2 and VAR3 typically contain the number of the source VR from which the element is being read. VAR1 contains the number of destination VR to which the element is being written.

Bits 5 and 6 of VAR 86 provide a column select (CS) signal on line 88, and bit 2 of VAR 87 provides a column select (CS) signal on line 88.
and 3 provide a row select (RS) signal on line 89.
The 7-bit address shown at 90 is used to address a particular one of the 128 locations in each array chip 85.

Each column (interleaved) as shown in Figure 9
are independently addressable. Since the same address is given to all 16 array chips 85 in one column, it is possible to write into one column and read from any one of the other three slave columns. It is possible. Data selection is done in the ring chip before gating into the stage registers. Short operands are presented in both parts of the half stage register (eg register 38).
For long operands, even numbered register elements go to the left half (0-31) and odd numbered register elements go to the right half (32-63).

Figures 10, 11, and 12 illustrate various uses of mask registers during vector processing. The vector mask register (VMR) is
It consists of 128 bits, and any one of them can be connected to VPU2.
It can be set or reset by processing with 0. It can be loaded with information from main memory or content stored in main memory at a rate of 8 bits per cycle. Maskuku・
The 128 bits in the register are the 128 bits stored in the VR.
corresponds to 1 element. As shown in Figure 10, the 128 bits of the mask register are further configured as 16 8-bit registers in the VMR array 9.
1. VMR specific binaries
Bit usage is selected by VMR address register 92 and bit selection wheel 93.
Bits 0-3 of VMR address register 92 are
Select one register in the VMR array 91,
Bits 4-6 select a particular one of the eight binary bits of the selected register. The selection of whether or not to use masking during arithmetic and logical processing is made by the set or reset state of vector mode trigger 94. Gate 95 is activated by vector mode trigger 94 to provide an output 96 when the particular mask bit selected by bit select 93 is a binary one.

The first group of instructions associated with the mask register consists of arithmetic instructions and circular instructions. vector·
When mode trigger 94 is off, each element of a vector is processed as the data flows and the results are retrieved at VR 57. However, if mode trigger 94 is on, processing proceeds as before, with one exception. ALU65
When the result of is passed to ALU output register 66 and valid bit 97 is set, signal 96 indicating a binary 1 mask bit gates valid bit 97 to valid bit 98 associated with VR fetch register 69. I can do it. binary 0
The vector mask register does not cause the ALU output results to be stored in the VR57. vector mask
Register address register 92 is incremented by one each time a result is stored in ALU output register 66.

As shown in FIG. 11, mask bits are used in an instruction called load extension. In this case, the vector elements are transferred from the CPU 22 to the data in register 37 by sequential address in main memory along with the data valid bit. For each propulsion pulse 54, the vector element address register associated with destination VR 57 is incremented by one along with VMR address register 92. Destination VR5 associated with vector mask bit that is binary 1
9 so that only element 7 receives data from the fetch register 69 and stores the element in VR 57.
At step 8, the data is set to valid.

In Figure 12, the order of the 128 elements of the vector is
It is read out from VR 57 to stage register 38 or lambda register 39 and sent to CPU 22 via interface line 35. However, only those elements having the corresponding mask bit of a binary 1 signaled to CPU 22 via line 99 are actually stored in main memory.

The manner in which VPU 20 provides correct information regarding exceptional or error conditions is shown in FIGS. 13 and 14. Various stages of data flow in VPU 20 are indicated in these figures with the same reference numerals as before. FIG. 13 shows the data path for storage access exceptions. The exception bit data path for storage access exceptions is parallel to the VPU 20 functional data path. There is one exception bit per data path stage. This exception data path is used for instructions that use vectors from main memory element 21 of FIG. If an access exception is detected in the storage device for a particular device, CPU 22
2 signal (normally 0) is set to 1, and this signal is sent to the VPU 20 together with the defective data. That signal is sent to the access exception data path starting at data in register 37 to begin the parallel data path at 43. This active bit flows with bad data and prevents that data from being retrieved by VR57. During the cycle in which bad data is retrieved, VPU 20
Signals an access exception to the CPU and prevents any further data fetching for this instruction.
The line 100 corresponds to the line labeled vector retrieval exception shown in FIG.
It is supplied to a branch wheel 48 associated with.

The access exception data path is formed by control lines according to the instruction being executed. Upon identification of an exception signal on line 100, CPU 22 microcode branches its processing loop to a common termination routine for all vector instructions encountering the exception.
In this routine, the microcode uses VIX, indicated by the count state of VEAR1, which represents the destination vector register, to calculate the storage address of the element with the exception. After updating the address information, the microcode fetches to the filing location and enters a standard interrupt handling routine. As shown in Fig. 13, generally, the ring 101 sends the access exception to the CPU 22 and the VR
For the data stored in the retrieval register 69
Prevent updating VR57. logic 101
A signal on line 102 of one of the three inputs of 3 indicates an access exception to an instruction that normally loads VR 57 from data-in register 37.
Signal line 103 indicates an access exception to data in ALU output register 66;
signals an access exception at a time prior to being retrieved from the multiplier/divider unit 76. The signal on line 105 relates to the operation exception described in FIG.

FIG. 14 shows the data path of the operation exception bit, which is a parallel portion of the data path of the VPU 200. The type of this exception is encoded in a 3-bit word. A 3-bit code is sent from VPU 20 to the status trigger of CPU 22 via line 45 previously discussed in connection with FIG. As shown at 106, the 3-bit exception code is not transferred to the CPU 22 when there is also an access exception shown in FIG.

As shown earlier, the arithmetic exception path is also VPU20
Parallelize the data paths of There are three different places in the data path where an operation exception can be found. Data is transferred from stage registers 71 and 72 to the fourth stage.
When transferred to the multiplier/divider unit 76, shown at 107 in the figure, a divide-by-zero and unnormalized operand exception is encountered. Multiply overflow and underflow exceptions may be encountered just before the multiply take register 79. Finally, in ALU65 in Figure 4,
ALU overflow, underflow, and weight loss exceptions are encountered just before the ALU fetch register 68.

The code for the various arithmetic exceptions sent from register 44 to CPU state 46 via line 45 is as follows.

001: Exponential overflow 010: Exponential underflow 011: Weight 100: Fixed point overflow 101: Unnormalized multiplication/division 110: Floating point division by 0 Thus, the above explanation provides the configuration of a vector processing device that can be added to the basic data processing device. The ordering of the vector processing unit disclosed is subject to active control in synchronization with the regular ordering of the microprogram control store. Additionally, a precise indication of the error or exception condition can be signaled to the underlying data processing system's interrupt handling mechanism. It is signaled by the vector processor controlling the entire storage of vector elements to place the vector processor in a known state for analysis by the underlying data processing system. The vector processing unit then provides coded signals to the basic data processing unit that indicate specific operation exceptions. Flexible and efficient utilization of the main memory of the basic data processing system is achieved by the vector processing system of the present invention through the use of vector mask registers and associated rings.

〔Effect of the invention〕

According to the present invention, it is possible to realize a vector processing device that performs a high-speed vector processing function by simply adding it to a general basic data processing device, and furthermore, once the elements in the vector storage of the vector processing device are accessed. This reduces processing time and allows effective use of the pipeline of the arithmetic unit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main interface between the vector processing device of the present invention and the central processing unit (CPU) of the basic data processing device, and FIG. 2 is a diagram showing the vector processing device including the present invention together with the existing data processing device. FIG. 3 is a diagram showing the signals applied to the microprogram branching circuit of the basic data processing device for vector processing; FIG. 4 shows the functional elements and data flow paths of the vector processing device of the present invention. 5 shows the controllable interconnection of these elements of the invention; FIG. 5 shows the data path of the vector processing device of the invention and the control of the data propulsion by microprogram control of the basic data processing device; FIG. FIG. 7 is an interconnection diagram of the elements of the vector processing device of the present invention for executing two representative vector instructions; FIG. 7 is a diagram showing the vector register arrangement and output data path of the vector processing device of the present invention; The figure also shows the arrangement of vector registers and input data paths of the vector processing device, FIG. 9 shows the addressing logic of the vector registers of the vector processing device, and FIG. 10 shows the operation during calculation in the vector processing device. FIG. 11 is a diagram illustrating the use of masking in conjunction with the elements of one vector during loading from main memory to a vector register; FIG. vector·
Figure 3 illustrates the use of masking in conjunction with the elements of a vector during the storage of elements from registers to main memory; FIG. FIG. 14 is a diagram illustrating the operation of the vector processing device of the present invention in response to an arithmetic exception indicating an error that occurred during arithmetic processing in the vector processing device of the present invention. FIG. 2 is a diagram showing the logic of a vector processing device. 20... Vector processing unit (VPU), 21...
Main memory, 22...Central processing unit (CPU), 25...
...Instruction preprocessing function (IPPF), 26...E function unit, 27...Data path, 29...Interface, 30...I element instruction queue, 31...Vector instruction register, 32...Q instruction buffer, 33
... Vector buffer register, 34 ... Stride register, 35 ... Data bus, 3
7...Data in register, 44...Exception code, 46...Status indicator, 47...Control memory,
48... Branching point, 49... Service request, 52...
...Data register, 53...Promotion.

Claims (1)

[Scope of Claims] 1. A storage device for storing instruction words and operands, and a microprogram control connected to the storage device and generating an execution control signal for controlling the execution of instructions retrieved from the storage device. a central processing unit (CPU) including the device; a vector processing unit (VPU) for processing vector data; and an interface means for connecting the CPU and the VPU, the interface means being one of the execution control signals.
interface means including a signal line for transferring a propulsion signal from the microprogram controller to the VPU, and controlling timing and gates in the VPU using the propulsion signal; the above
A data processing device having vector processing capability, characterized in that vector processing in a VPU is synchronized with the CPU.