JPH03280550A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To unnecessitate a spacer oxide film and the like between an upper layer gate electrode and a lower layer gate electrode, by constituting a gate electrode as a two-layered structure, and utilizing the difference of the etching rates for dry etching of the materials constituting said structure. CONSTITUTION:In the element isolation region on the main surface of a P-type silicon substrate 1, a field oxide film 2, a channel stopper 3, a gate oxide film 4, and an N-type poly silicon film 5 are formed, and a tungsten silicide film 6 is deposited. After a photo resist film 7 is formed in the desired shape of a gate electrode, the tungsten silicide film 6 is etched with an RIE equipment, thereby forming a tungaten silicide electrode 6a. A low concentration source.drain layer 8 and a CVD oxide film 9 are deposited; etching-back is performed with the RIE equipment, thereby forming a spacer oxide film 6a only on the side wall of a tungsten silicide electrode 6a. Next, a polysilicon gate electrode 5a is formed by etching the poly silicon film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an integrated circuit device, and particularly to a method of manufacturing a MOS transistor having an LDD structure.

[Conventional technology]

A method of manufacturing a MOS transistor having an improved LDD structure in a conventional MOS transistor having an LDD structure will be explained using step-by-step cross-sectional views shown in FIGS. 2(a) to 2(e).

First, a field oxide film 2 is selectively formed on the main surface of a silicon substrate 1. A gate oxide film 4 is formed.

At this time, a channel stopper 3 is also formed directly under the field oxide film 2. Next, a first polysilicon film 13 is deposited, and a thin stopper oxide film 15 is formed on the surface of the first polysilicon film 13.
After forming a second polysilicon film and a first CVD oxide film, the first CVD oxide film is processed into a mask oxide film 16 having a desired gate electrode shape using photolithography technology. Using this as a mask, the second polysilicon film is etched by isotropic plasma etching to form a second polysilicon gate electrode 4k14 [FIG. 2(a)].

Next, a source/drain low concentration layer 8 is formed by ion implantation [FIG. 2(b)], and a second CVD oxide film 17 is deposited [FIG. 2(C)].

Next, the second CV is etched by reactive ion etching (RIE).
The D oxide film 17 is etched back to form a spacer oxide film 17a made of a second CVDoI film on the side surface of the second polysilicon gate electrode 14. Subsequently, mask oxide film 16. Using the spacer oxide film 17a as a mask, the first polysilicon Jli 13 and gate oxide film 4 are etched to form a first polysilicon gate electrode 13a.
Figure 2(d)').

Next, the source/drain high concentration layer 10 is formed by ion implantation.
(Fig. 2(e)).

[Problem to be solved by the invention]

In the conventional manufacturing method described above, when etching the second polysilicon film, a thin stopper oxide film formed on the first polysilicon film is used as a striker, so if this stopper oxide film is too thin, It does not play the role of a stopper, and conversely, if the stopper oxide film is too thick, it will prevent electrical conduction between the first polysilicon gate electrode and the second polysilicon electrode. Therefore, it is necessary to strictly control the upper and lower limits of the thickness of this stopper oxide film, which poses a major obstacle in manufacturing.

In addition, when forming the second polysilicon gate electrode under the mask oxide film, side etching is intentionally performed, which tends to create cavities when forming the spacer oxide film in the next process, resulting in device reliability. There is also the risk of having a negative impact on sexuality.

[Means to solve the problem]

The method for manufacturing an integrated circuit device of the present invention includes forming a first conductive film, a second conductive film, and a second conductive film on the main surface of a semiconductor substrate having a selectively formed element isolation oxide film and a gate oxide film.
a step of depositing a second conductive film, a step of forming a second gate electrode made of a second conductive film by etching the photoresist film patterned into a desired gate electrode shape; and a step of forming a second gate electrode made of a second conductive film by ion implantation. , a step of forming a low concentration layer for the source/drain, and a step of peeling off the photoresist film, depositing an insulating film, and then forming a spacer made of the above insulating film on the side wall of the second gate electrode by etching back. A step of forming a first gate electrode made of a first conductive film by etching using the second gate electrode and spacer as a mask; A step of forming a highly concentrated source/drain layer by ion implantation. It has and .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(h) are sectional views in the order of steps of a first embodiment of the present invention.

In this example, the first conductive film is a polysilicon film, and the second conductive film is a polysilicon film.
A tungsten silicide film, a first goo 1 on the conductive film
~N-channel MO using a polysilicon gate electrode as the electrode and a tungsten silicide electrode as the first gate electrode
Let's talk about the S transistor.

First, a selective oxidation method (LOGO8) is applied to the element isolation region on the main surface of the P-type silicon substrate 1 to form a 0.8-1.0μ
A field oxide film 2 having a thickness of m is formed. In the element isolation region, a channel stopper 3 is formed in advance by ion implantation, and then a gate oxide film 4 of 150 to 250 layers is deposited in a dry oxygen atmosphere at 900 to 950°C.
form. After that, a film thickness of 2000 was obtained using the LPCVD method.
A polysilicon film of ~3,000 layers is deposited, and phosphorus is diffused to form an N-type polysilicon film 5. Subsequently, a tungsten silicide film 6 having a thickness of 2,000 to 3,000 wafers is deposited by sputtering [FIG. 1(a)]. Note that tungsten silicide satisfies WS i x (2≦X≦3
).

Next, a photoresist film 7 is formed in the shape of a desired gate electrode using photolithography technology, and then the tungsten silicide film 6 is etched using a parallel plate type reactive ion etching (RIE) device to form a tungsten silicide electrode 6a. [Figure 1(b)]
. As the reaction gas, Cβ and F have a sufficiently large etching rate of tungsten silicide compared to polysilicon.
A mixed gas containing

Next, phosphorus ion implantation was performed at 200 to 300 keV, 5X1
012 to 5×10 at a thickness of 3 cm −2 to form a source/drain low concentration layer 8 [FIG. 1(C)].

Next, after the photoresist film 7 is ashed by 02 plasma, a CVD oxide film 9 with a thickness of 2,000 to 4,000 thick is deposited by the LPCVD method (FIG. 1(d)).

Subsequently, etchback was performed using a parallel plate type RIE apparatus using a mixed gas of a gas containing F and 02 gas,
A spacer oxide film 9a made of a CVD oxide film is formed only on the side wall of the tungsten silicide electrode 6a [Fig.
e)].

Next, using the tungsten silicide electrode 6a and the spacer oxide film 9a as masks, a gas containing (1', F and N2
The polysilicon film 5 is etched using a parallel plate type RIE apparatus using a mixed gas with the polysilicon gate electrode 5a (FIG. 1(f)).

Next, arsenic ion implantation was performed at 40 to 60 keV.

1 x 1015 to 5 x 10"cm-2 to form the source/drain high concentration layer 10 [Fig. 1(g)]
.

Thereafter, according to the usual manufacturing method, as the glabellar insulating film 11,
BPSG is deposited to a thickness of 0.6 to 0.8 μm. Interlayer insulation II! After opening a contact hole in 11, a metal film of /l-1% Si is deposited by sputtering and patterned into a desired shape to form wiring metal 12 [Fig. 1 (h)]
).

In the present invention, it is sufficient that the selectivity ratio between the second gate electrode and the first gate electrode during reactive ion etching is 2 or more.

In the second embodiment of the present invention, a polysilicon film is used for the first gate electrode, and a tungsten film is used for the second gate electrode. The manufacturing process is similar to that of the first embodiment, so a description thereof will be omitted.

〔Effect of the invention〕

As explained above, the present invention provides a two-layer structure for the gate electrode, and utilizes the difference in the etch rate of the material used to refine the structure to oxidize the spacer between the upper and lower gate electrodes. MOS ? - It becomes possible to easily form transistors with high precision.

[Brief explanation of drawings]

1(a) to (h) are step-by-step cross-sectional views of the first embodiment of the present invention, and FIG. 2(a)-(e) are step-by-step cross-sectional views showing a conventional method for manufacturing an integrated circuit device. It is. 1... Silicon substrate, 2... Field oxide film, 3
... Channel stopper, 4... Gate oxide film,
5... Polysilicon film, 5a... Polysilicon gate electrode, 6... Tungsten silicide film, 6a...
・Tungsten silicide gate electrode, 7... Photoresist film, 8... Source/drain low concentration layer, 9.
...CVD oxide film, 9a, 17a... Spacer oxide film, 10... Source/drain high concentration layer, 11... Insulating film between eyebrows, 12... Wiring metal, 13... First vol. silicon film, 13a... first polysilicon gate electrode, 14... second polysilicon gate electrode, 15.
...Stopper oxide film, 16...Mask oxide film, 17
...Second CVD oxide film.

Claims (1)

[Claims] 1. On the main surface of a semiconductor substrate having a selectively formed element isolation oxide film and a gate oxide film, a first conductive film;
a step of depositing a second conductive film; a step of forming a second gate electrode made of the second conductive film by etching a photoresist film patterned into a desired gate electrode shape; A step of forming a low concentration source/drain layer by ion implantation, and after peeling off the photoresist film and depositing an insulating film,
a step of forming a spacer made of the insulating film on the side wall of the second gate electrode by etchback; and a step of forming the spacer made of the first conductive film by etching using the second gate electrode and the spacer as a mask. A method for manufacturing an integrated circuit device, comprising the steps of: forming a first gate electrode; and forming a source/drain high concentration layer by ion implantation. 2. Manufacturing the integrated circuit device according to claim 1, wherein the first conductive film is a polysilicon film, and the second conductive film is a high melting point metal film or a high melting point metal silicide film. Method.