JPH03280716A - Dynamic frequency divider - Google Patents
Dynamic frequency dividerInfo
- Publication number
- JPH03280716A JPH03280716A JP8270090A JP8270090A JPH03280716A JP H03280716 A JPH03280716 A JP H03280716A JP 8270090 A JP8270090 A JP 8270090A JP 8270090 A JP8270090 A JP 8270090A JP H03280716 A JPH03280716 A JP H03280716A
- Authority
- JP
- Japan
- Prior art keywords
- input
- frequency
- frequency divider
- resistor
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000295 complement effect Effects 0.000 claims abstract description 13
- 230000005669 field effect Effects 0.000 claims description 8
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005513 bias potential Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はダイナミック型分周器に関し、特にＧａＡｓ
（ガリウム・ヒ素）ＦＥＴを基本素子としたダイナミッ
ク型分周器の回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic frequency divider, and in particular to a GaAs frequency divider.
This invention relates to a dynamic frequency divider circuit using a (gallium arsenide) FET as a basic element.
従来のこの種のＧ ａ Ａ ｓダイナミック型分周器は
、第３図に示すように、ダイナミック型分周器本体１４
と、バイアス発生用直列抵抗５，６と、高抵抗１０と、
入力端子１と、相補入力端子２とを含み、電源電圧端子
１２．１３間にバイアスがかけられる。ここで、分周器
本体１４は、Ｇ ａ Ａ ｓ電界効果トランジスタ（Ｆ
ＥＴ）２０〜２９を有する。本考案分周器は、抵抗分割
により、入力及び相補入力のバイアスを発生させている
。As shown in FIG.
, series resistances 5 and 6 for bias generation, high resistance 10,
It includes input terminal 1 and complementary input terminal 2, and is biased between power supply voltage terminals 12,13. Here, the frequency divider main body 14 is a GaAs field effect transistor (F
ET) 20-29. The frequency divider of the present invention generates bias for the input and complementary inputs by resistor division.
前述した従来のＧ ａ Ａ ｓダイナミック型分周器で
は、動作周波数範囲が、スタティック型と比べて狭く、
入力及び相補入力のバイアス電圧を高くずれは、動作周
波数領域が高周波側へずｈ７、逆にバイアス電圧を低く
すれば低周波側へとずｔしるという特性があり、抵抗分
割によりバイアス電圧を固定１−ていた為、広い動作周
波数領域が得られないという欠点がある。In the conventional GaAs dynamic type frequency divider mentioned above, the operating frequency range is narrower than that of the static type.
If the bias voltage of the input and complementary inputs is shifted high, the operating frequency range will shift to the high frequency side, and conversely, if the bias voltage is lowered, the operating frequency range will shift to the low frequency side. Since it is fixed at 1-, there is a drawback that a wide operating frequency range cannot be obtained.
本発明の構成は、入力端子と相補入力端子とを設け、方
すウム・ヒ素電界効果トランジスタを基本素子とする分
周器本体を第１．第２の電源電圧間に備えたダイナミッ
ク型分周器において、前記入力端子から増幅回路、第１
のキャパシタンスを介した後にゲート入力とする電界効
果トランジスタと、前記第１．第２の電源電圧間に第１
．第２の抵抗の直列体を接続Ｌ、その共通接続点を前記
ケ−１・入力となし、前記電界効果ｌ・ランジスタの一
電極を定電位に接続し、かつ他電極を第３．第４の抵抗
の一端に接続１〜、前記第３の抵抗の他端を前記第１の
電源電圧に接続１〜、前記第４の抵抗の他端を第２のキ
ャパシタンスの一端に接続し、前記第２のキャパシタン
スの他端に前記定電位を接続し、前記第４の抵抗の他端
に第５の抵抗を介ｔ７た後に前記入力端子、前記相補入
力端子を接続１〜たことを特徴とする。The structure of the present invention is such that an input terminal and a complementary input terminal are provided, and a frequency divider body whose basic element is a galvanic arsenic field effect transistor is connected to a first frequency divider body. In the dynamic frequency divider provided between the second power supply voltage, the input terminal connects the amplifier circuit to the first power supply voltage.
a field effect transistor whose gate is input after passing through a capacitance of the first field effect transistor; between the second power supply voltage and the first
．． The series body of the second resistor is connected L, their common connection point is the input of the case 1, one electrode of the field effect transistor is connected to a constant potential, and the other electrode is connected to the 3rd. Connecting 1~ to one end of the fourth resistor, connecting the other end of the third resistor to the first power supply voltage 1~, connecting the other end of the fourth resistor to one end of the second capacitance, The constant potential is connected to the other end of the second capacitance, and the input terminal and the complementary input terminal are connected to the other end of the fourth resistor through a fifth resistor after t7. shall be.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例のダイナミック型分周器
な示す回路図である。FIG. 1 is a circuit diagram showing a dynamic frequency divider according to a first embodiment of the present invention.
第１図において、本実施例の分周器は、入力端子１を入
力とする増幅回路３と、抵抗５，６の分割点と増幅回路
３の出力との間の０．５ｐＦのキャパシタ４と、ＦＥＴ
８と、負荷抵抗７と、２にΩのｉ％ｉ抗９と、２ｐＦの
バイパス用キャパシタ】１とが設けられており、その他
の部分は第３図と同一の算用数字を伺１−て、同様な部
分であることを示している。In FIG. 1, the frequency divider of this embodiment includes an amplifier circuit 3 whose input is input terminal 1, a 0.5 pF capacitor 4 between the dividing point of resistors 5 and 6, and the output of the amplifier circuit 3. , FET
8, a load resistor 7, an Ω i%i resistor 9, and a 2 pF bypass capacitor 1 are provided at 2, and the other parts have the same arithmetic numbers as in FIG. This shows that they are similar parts.
ここで、ＦＥＴ８のゲートは、入力端子１より、増幅回
路３．キャパシタ４を介して接続され、さらにこのゲー
トはバイアス発生用抵抗５，６を介してそれぞれ電源電
圧端子１２．１３に接続される６ＦＥＴ８のソースは接
地され、ドレインは負荷抵抗７を介して電源電圧端子１
２に接続され、さらにとのドレインは高抵抗９．バイパ
ス用キャパシタ１１．さらに２にΩの高抵抗１０を介し
て、入力端子１，２に接続される。入力端子１．２は、
ダイナミック型分周器１４本体に接続される。増幅回路
３０周波数特性を、低周波入力時にゲイン大、高周波入
力時にゲイン小となるようにし、さらにＦＥＴ８のゲー
ト入力電位が低（Ｌ ｏ ｗ）レベル時には、ＦＥＴ８
がカットオフするように、抵抗５，６によりゲートバイ
アスを設定する。これにより、入力周波数が低くなるに
従い、ＦＥＴ入力振幅が大きくなり、ドレイン端のＤＣ
電位が下がり、入力及び相補入力バイアス電位が低くな
ることで、低周波領域での動作が可能となる。つまり、
入力周波数に応じて、バイアス電位が変化することで広
い動作領域が得られる。Here, the gate of FET8 is connected from input terminal 1 to amplifier circuit 3. The source of the 6FET 8 is connected to the power supply voltage terminal 12 and 13 through the capacitor 4 and the gate thereof is connected to the power supply voltage terminal 12 and 13 through the load resistor 7. terminal 1
2, and the drain of 9. is connected to high resistance. Bypass capacitor 11. Furthermore, it is connected to input terminals 1 and 2 via a high resistance 10 of Ω. Input terminals 1.2 are
It is connected to the main body of the dynamic type frequency divider 14. The frequency characteristics of the amplifier circuit 30 are set so that the gain is large when a low frequency is input, and the gain is small when a high frequency is input.Furthermore, when the gate input potential of the FET8 is at a low level,
The gate bias is set by resistors 5 and 6 so that the voltage is cut off. As a result, as the input frequency decreases, the FET input amplitude increases, and the DC at the drain end increases.
By lowering the potential and lowering the input and complementary input bias potentials, operation in a low frequency region becomes possible. In other words,
A wide operating range can be obtained by changing the bias potential depending on the input frequency.
第２図は本発明の第２の実施例のダイナミック型分周器
を示す回路図である。FIG. 2 is a circuit diagram showing a dynamic frequency divider according to a second embodiment of the present invention.
第２図において、本実施例の分周器は、第１図の回路に
、抵抗１５を追加した回路であり、その他の部分は第１
図と同様である。In FIG. 2, the frequency divider of this embodiment is a circuit in which a resistor 15 is added to the circuit of FIG.
It is similar to the figure.
第２図において、バイアス電圧調整用抵抗１５をＦＥＴ
８と並列に入れることで、入力端子１及び相補入力端子
２のバイアス電圧の入力周波数依存性を調整することが
できる。In FIG. 2, the bias voltage adjustment resistor 15 is replaced by an FET.
8 in parallel, the input frequency dependence of the bias voltages of the input terminal 1 and the complementary input terminal 2 can be adjusted.
本実施例では、前記バイアス電位を入力周波数に応じて
、自動的に変化させ、動作周波数範囲を広くとることが
出来る。In this embodiment, the bias potential is automatically changed according to the input frequency, so that the operating frequency range can be widened.
以上説明したように本発明は、入力周波数に応じて、入
力及び相補入力バイアス電位を高周波入力時には高電位
に、低周波入力時には低電位に、ＩＣ内部で自動的に変
化させることにより、広い動作周波数範囲が得られると
いう効果がある。As explained above, the present invention has a wide range of operability by automatically changing the input and complementary input bias potentials inside the IC to a high potential when a high frequency input is made and to a low potential when a low frequency input is made, depending on the input frequency. This has the effect of providing a frequency range.
第１図は本発明の第１の実施例のダイナミック型分周器
の回路図、第２図は本発明の第２の実施例の回路図、第
３図は従来のダイナミック型分周器の回路図である。
１・・・・・・入力端子、２・・・・・・相補入力端子
、３・・・・・・増幅回路、４・・・・・・キャパシタ
、５，６・・・・・・バイアス発生用抵抗、７・・・・
・・負荷抵抗、８・・・・・・ＦＥＴ、９．１０・・・
・・・高抵抗、１１・・・・・・バイパス用キャパシタ
、１２．１３・・・・・・電源電圧端子、１４・・・・
・・ダイナミック型分周器本体。FIG. 1 is a circuit diagram of a dynamic frequency divider according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional dynamic frequency divider. It is a circuit diagram. 1... Input terminal, 2... Complementary input terminal, 3... Amplifier circuit, 4... Capacitor, 5, 6... Bias Generation resistance, 7...
...Load resistance, 8...FET, 9.10...
...High resistance, 11...Bypass capacitor, 12.13...Power supply voltage terminal, 14...
・Dynamic frequency divider body.
Claims (1)
効果トランジスタを基本素子とする分周器本体を第１、
第２の電源電圧間に備えたダイナミック型分周器におい
て、前記入力端子から増幅回路、第１のキャパシタンス
を介した後にゲート入力とする電界効果トランジスタと
、前記第１、第２の電源電圧間に第１、第２の抵抗の直
列体を接続し、その共通接続点を前記ゲート入力となし
、前記電界効果トランジスタの一電極を定電位に接続し
、かつ他電極を第３、第４の抵抗の一端に接続し、前記
第３の抵抗の他端を前記第１の電源電圧に接続し、前記
第４の抵抗の他端を第２のキャパシタンスの一端に接続
し、前記第２のキャパシタンスの他端に前記定電位を接
続し、前記第４の抵抗の他端に第５の抵抗を介した後に
前記入力端子、前記相補入力端子を接続したことを特徴
とするダイナミック型分周器。A first frequency divider main body is provided with an input terminal and a complementary input terminal, and has a gallium arsenide field effect transistor as a basic element.
In a dynamic frequency divider provided between a second power supply voltage, the input terminal is connected to an amplifier circuit, a field effect transistor whose gate is input after passing through a first capacitance, and the first and second power supply voltages. A series body of first and second resistors is connected to , the common connection point thereof is used as the gate input, one electrode of the field effect transistor is connected to a constant potential, and the other electrode is connected to the third and fourth resistors. the second capacitance; the other end of the third resistor is connected to the first power supply voltage; the other end of the fourth resistor is connected to one end of the second capacitance; A dynamic frequency divider, characterized in that the constant potential is connected to the other end of the fourth resistor, and the input terminal and the complementary input terminal are connected to the other end of the fourth resistor via a fifth resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8270090A JPH03280716A (en) | 1990-03-29 | 1990-03-29 | Dynamic frequency divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8270090A JPH03280716A (en) | 1990-03-29 | 1990-03-29 | Dynamic frequency divider |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280716A true JPH03280716A (en) | 1991-12-11 |
Family
ID=13781682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8270090A Pending JPH03280716A (en) | 1990-03-29 | 1990-03-29 | Dynamic frequency divider |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280716A (en) |
-
1990
- 1990-03-29 JP JP8270090A patent/JPH03280716A/en active Pending
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