JPH03280764A - Plural-unit configuration system - Google Patents

Plural-unit configuration system

Info

Publication number
JPH03280764A
JPH03280764A JP8260990A JP8260990A JPH03280764A JP H03280764 A JPH03280764 A JP H03280764A JP 8260990 A JP8260990 A JP 8260990A JP 8260990 A JP8260990 A JP 8260990A JP H03280764 A JPH03280764 A JP H03280764A
Authority
JP
Japan
Prior art keywords
unit
processor
inter
exchange
exchange unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8260990A
Other languages
Japanese (ja)
Inventor
Kazutaka Morita
和孝 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8260990A priority Critical patent/JPH03280764A/en
Publication of JPH03280764A publication Critical patent/JPH03280764A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To use a line efficiently by interconnecting a channel switch accommodated in plural electronic exchange units and a processor of an exchange unit between the units by a high speed bus. CONSTITUTION:An electronic exchange unit 10 has a channel switch 11, a processor 12, a connection information memory 13 and a unit exchange unit 20 has a channel switch 21 and a control processor 22. The switches 11, 21 act their function under the control of the processors 12, 22, and the processor 12 has an exchange function and a function of sending and receiving information with other processor and of interunit exchange. Then the memory 13 stores the state of connection of the units 10, 20. Then the channel 31 is connected to the switch 11 and the processor 22 sends/receives the information of the switch 21 and is connected to the processor 12 by a high speed bus 32. Since the state of operation of line with each unit 10 connecting to the unit 20 is recognized, the line is efficiently used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、複数の電f′9.換ユニット°て゛構成する
複数ユニット構成システムに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a plurality of electric currents f'9. The present invention relates to a multi-unit system configured with exchange units.

〔従来の技術) 従来の複数のユニット構成システムは、複数の電子交換
ユニットがそれぞれ独立した構成をもって、網を形成l
−でいた。
[Prior Art] In a conventional multiple unit configuration system, a plurality of electronic switching units each have an independent configuration to form a network.
-It was.

〔発明が解決1−ようとする課題〕 」二連し、た従来の複数コーニッl−構成システムは、
構成する電子交換ユニットが独立l〜ているのて、I・
うしツクが片寄った場合に迂回による回線使用が増加1
−1回線の効果的使用が阻害されるという問題点があっ
た。
[Problem to be solved by the invention 1] The conventional multiple cornice structure system with two series
Since the constituent electronic exchange units are independent, I.
When Ushitsuk is lopsided, line usage increases due to detours1
- There was a problem in that the effective use of one line was hindered.

本発明の目的は、上記問題点を解決17な複数ユニット
構成システムを提供することにある。
An object of the present invention is to provide a multi-unit configuration system that solves the above-mentioned problems.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による複数1::ツト構成システムの基本構成は
、複数の電子交換ユニツ)−・で構成する複数ユニット
構成システム(1,:おいて、前記電子交換ユニッ1−
のぞれぞれに収容し接続する通信路を収容し接続する通
信路スイッチと、前記電子交換ユニッ1〜のブロセッナ
に高速バスで接続する情報を授受して前記通信路スイッ
チを制御する制御プロセッサとを有するユニツ1−・間
交換ユニットを@メる。
The basic configuration of the multiple unit configuration system according to the present invention is a multiple unit configuration system (1,:) consisting of a plurality of electronic exchange units).
a communication path switch that accommodates and connects the communication paths that are accommodated and connected to each, and a control processor that controls the communication path switch by transmitting and receiving information to connect to the Brossena of the electronic exchange units 1 to 1 through a high-speed bus. @mail the exchange unit between unit 1 and having the unit.

この基本構成に記載の電子交換ユニットの一つの具体化
構成は4電子交換ユニットのそれぞれが、ユニッ1−間
通信路の接続状況をユニット、間交換ユニットから受信
して記憶する接続情報メモリと、ユニット間交換ユニッ
)・の駆動禁止状態99例ノば#W発生、の通知信号珪
かはこの解除信号をユニッl−間交換ユニットから受信
し電子交換ユニットのユニット間接続を規制または規制
解除すると共に、回線解放の条件にあれば、ユニッ■・
間の接続状況を前記接続情報、メモリから読出して解放
処理を行ない、処理終了をユニット間交換ユニッ■・に
通知するプロセッサとを有する。
One specific configuration of the electronic switching unit described in this basic configuration is that each of the four electronic switching units includes a connection information memory that receives and stores the connection status of the communication path between the units and the inter-unit switching unit; Notification signal of 99 instances of #W occurrence in drive prohibition state (inter-unit exchange unit).The unit receives this release signal from the unit-to-unit exchange unit and restricts or releases the restriction on the inter-unit connection of the electronic exchange unit. In addition, if the conditions for line release are met, unit
and a processor that reads the connection status between the units from the connection information and the memory, performs release processing, and notifies the inter-unit exchange unit of the completion of processing.

また、基本構成に記載のユ、ニット間交換ユニットの具
体的な−っの構成は、ユニット間交換ユニットの駆動監
視状態、例えば障害発生の通知信号または、:の解除信
号を電子交換ツーニットへ送信すると共に、解放の処理
終了の通知を電子交換ユニッ1=−から受信したときこ
の通知を全ての電子交換ユニツI−へ通知する制御プロ
セッサを有する。
In addition, the specific configuration of the inter-unit exchange unit described in the basic configuration is to send a drive monitoring status of the inter-unit exchange unit, such as a failure notification signal or a cancellation signal to the electronic exchange unit. At the same time, it has a control processor that notifies all electronic exchange units I- of the notification of completion of release processing when it is received from electronic exchange unit 1=-.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の一実施例を示すブロック図、また第
2図は第1図による主要動作手順の一例を示すフローチ
ャートである。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a flowchart showing an example of the main operation procedure according to FIG.

第】−図に示すように、複数の電子交換ユニット10は
ユニット間交換ユニット20と通信路31および光ケー
ブルによる高速バス32で接続される。
As shown in the figure, a plurality of electronic exchange units 10 are connected to an inter-unit exchange unit 20 by a communication path 31 and a high-speed bus 32 using an optical cable.

電子交換ユニット10は通信路スイッチ11゜プロセッ
サ]2.および接続情報メモリ13を有し、ユニット間
交換ユニッ■・20は通信路スイッチ21および制御プ
ロセッサ22を有する。
The electronic exchange unit 10 is a communication path switch 11゜processor]2. and a connection information memory 13, and the inter-unit exchange unit 20 has a communication path switch 21 and a control processor 22.

通信路スイッチ11はプロセッサ12の制御により機能
を発揮する。プロセッサ12は通常の交換機能を主とし
、且つユニット間交換ユニット2Oの制御プロセッサ2
2と情報を授受してユニッI−間交換の機能も有する。
The communication path switch 11 functions under the control of the processor 12. The processor 12 mainly has a normal exchange function, and also serves as a control processor 2 for the inter-unit exchange unit 2O.
It also has the function of exchanging information between units I and 2 by exchanging information with each other.

接続情報メモリ13は電子交換ユニット]0がユニッl
=間交換ユニット20と接続中の状況を記憶する。
Connection information memory 13 is electronic exchange unit] 0 is unit
=Memorize the status of connection with the inter-exchange unit 20.

通信路スイッチ21は制御プロセッサ22の制御により
機能を発揮するが、収容接続する通信路31は各電子交
換ユニット10の通信路スイッチ11に接続する。制御
プロセッサ22は通信路スイッチ21と情報の授受をす
ると共に、高速バス32により各電子交換ユニット]0
のプロセッサ12に接続する。
The communication path switch 21 functions under the control of the control processor 22, and the communication path 31 to be accommodated and connected is connected to the communication path switch 11 of each electronic switching unit 10. The control processor 22 sends and receives information to and from the communication path switch 21, and also communicates with each electronic switching unit via the high-speed bus 32.
is connected to the processor 12 of the computer.

上述の構成により通常の交換機能は実行できるが、ユニ
ット間交換ユニットに障害などで接続規制が施行された
とき、この接続規制の解除によるユニット間交換ユニッ
トの再開時にはこの時点まで使用中の回線の解放処理が
必要となり、これが記憶情報の誤りを防止する。
Although normal switching functions can be performed with the above configuration, when connection restrictions are enforced due to a failure in the unit-to-unit exchange unit, when the connection restriction is lifted and the unit-to-unit exchange unit is restarted, the lines that have been in use up to that point are A release process is required, which prevents errors in stored information.

これについて、第2図に第1図を併せ参照して説明する
。ユニット間交換ユニット2oに障害が発生したとき、
制御プロセッサ22は障害発生を検出(101)して、
駆動禁止を高速バス32を介して、電子交換ユニット1
0のプロセッサ12へ通知(102)する。駆動禁止を
受信(103)したプロセッサ12はユニット間接続を
規制(104)する。手順102で駆動禁止を通知した
のち、制御プロセッサ22は障害の回復を認知すること
により駆動禁止の解除を高速バス32を介してプロセッ
サ12に通知(105)する。駆動監視解除を受信(1
06)したプロセッサ12は、ユニット間接続の規制を
解除(107)L、回線の接続状況を接続情報メモリ1
3で調整(108)する、調整により回線解放が必要(
109)な場合、プロセッサ12は回線の解放処理(1
10)をしたのち処理の終了を高速バス32を介して制
御プロセッサ22へ通知(111)する。プロセッサ2
2は回線の処理終了をすべての電子交換ユニット10か
ら受信(112)Lなとき、すべての電子交換ユニット
10のプロセッサ12へ全処理終了を通知(113)す
る。プロセッソ12は全処理終了の通知を受信(114
)して、ユニット間接続を開始する。
This will be explained with reference to FIG. 2 and FIG. 1 together. Inter-unit exchange When a failure occurs in unit 2o,
The control processor 22 detects the occurrence of a failure (101) and
Drive prohibition via express bus 32, electronic exchange unit 1
0 processor 12 is notified (102). The processor 12 that receives the driving prohibition (103) regulates inter-unit connections (104). After notifying drive prohibition in step 102, the control processor 22 notifies the processor 12 via the express bus 32 of the cancellation of the drive prohibition upon recognizing recovery from the failure (105). Drive monitoring cancellation received (1
06), the processor 12 releases the restriction on connections between units (107)L, and stores the line connection status in the connection information memory 1.
Adjust in step 3 (108), it is necessary to release the line by adjusting (108).
109), the processor 12 performs line release processing (1
10), the end of the process is notified to the control processor 22 via the high-speed bus 32 (111). processor 2
2 receives the completion of line processing from all the electronic switching units 10 (112), and when it is L, notifies the processors 12 of all the electronic switching units 10 of the completion of all processing (113). The processor 12 receives the notification of completion of all processing (114
) to start the inter-unit connection.

すなわち、回線の接続状態をほぼ初期状態に戻してから
ユニット間接続を再開することになる。
In other words, the connection between the units is restarted after returning the line connection state to almost its initial state.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、複数の電子交換ユニット
の通信路スイッチおよびプロセッサのそれぞれを通信路
および高速バスのそれぞれでユニット間交換ユニットの
通信路スイッチおよび制御プロセッサのそれぞれに接続
するように構成することにより、ユニット間交換ユニッ
トが接続する各電子交換ユニットとの回線使用状況から
効率よく回線を使用できる効果がある。
As described above, the present invention is configured such that each of the communication path switches and processors of a plurality of electronic exchange units is connected to each of the communication path switches and control processor of an inter-unit exchange unit by a communication path and a high-speed bus, respectively. By doing so, there is an effect that the line can be used efficiently based on the line usage status with each electronic exchange unit to which the inter-unit exchange unit connects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の複数ユニット構成システムの一実施例
を示すブロック図、第2図は第1図における主要動作手
順の一例を示ずフローチャートである。 10・・・電子交換ユニット、11.21・・・通信路
スイッチ、 2゜ 2・・・プロセッサ、 3・・・接続 情報メモリ、 1・・・通信路、 2・・・高速バス。
FIG. 1 is a block diagram showing an embodiment of a multi-unit system according to the present invention, and FIG. 2 is a flowchart illustrating an example of the main operation procedure in FIG. 1. DESCRIPTION OF SYMBOLS 10...Electronic exchange unit, 11.21...Communication path switch, 2.2...Processor, 3...Connection information memory, 1...Communication path, 2...High speed bus.

Claims (1)

【特許請求の範囲】 1、複数の電子交換ユニットで構成する複数ユニット構
成システムにおいて、前記電子交換ユニットのそれぞれ
に収容し接続する通信路を収容し接続する通信路スイッ
チと、前記電子交換ユニットのプロセッサに高速バスで
接続する情報を授受して前記通信路スイッチを制御する
制御プロセッサとを有するユニット間交換ユニットを備
えることを特徴とする複数ユニット構成システム。 2、請求項1記載の電子交換ユニットのそれぞれが、ユ
ニット間通信路の接続状況をユニット間交換ユニットか
ら受信して記憶する接続情報メモリと、ユニット間交換
ユニットの駆動禁止状態、例えば障害発生、の通知信号
またはこの解除信号をユニット間交換ユニットから受信
し電子交換ユニットのユニット間接続を規制または規制
解除すると共に、回線解放の条件にあれば、ユニット間
の接続状況を前記接続情報メモリから読出して解放処理
を行ない、処理終了をユニット間交換ユニットに通知す
るプロセッサとを有することを特徴とする請求項1記載
の複数ユニット構成システム。 3、請求項1記載のユニット間交換ユニットは、ユニッ
ト間交換ユニットの駆動監視状態、例えば障害発生の通
知信号またはこの解除信号を電子交換ユニットへ送信す
ると共に、解放の処理終了の通知を電子交換ユニットか
ら受信したときこの通知を全ての電子交換ユニットへ通
知する制御プロセッサを有することを特徴とする請求項
1記載の複数ユニット構成システム。
[Scope of Claims] 1. In a multi-unit system composed of a plurality of electronic switching units, a communication path switch that accommodates and connects a communication path that is accommodated and connected to each of the electronic switching units; 1. A system comprising a plurality of units, comprising an inter-unit exchange unit having a control processor that transmits and receives information connected to a processor via a high-speed bus and controls the communication path switch. 2. Each of the electronic exchange units according to claim 1 includes a connection information memory that receives and stores the connection status of the inter-unit communication path from the inter-unit exchange unit, and a drive prohibited state of the inter-unit exchange unit, such as when a failure occurs. receiving the notification signal or this release signal from the inter-unit exchange unit to restrict or release the restriction on the inter-unit connection of the electronic exchange unit, and if the line release condition is met, read out the connection status between the units from the connection information memory. 2. The multi-unit system according to claim 1, further comprising a processor that performs release processing and notifies the inter-unit exchange unit of completion of the processing. 3. The unit-to-unit exchange unit according to claim 1 transmits the drive monitoring state of the unit-to-unit exchange unit, for example, a notification signal of failure occurrence or a cancellation signal thereof, to the electronic exchange unit, and also sends a notification of completion of release processing to the electronic exchange unit. 2. The multi-unit system of claim 1, further comprising a control processor that notifies all electronic switching units of this notification when received from the unit.
JP8260990A 1990-03-29 1990-03-29 Plural-unit configuration system Pending JPH03280764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8260990A JPH03280764A (en) 1990-03-29 1990-03-29 Plural-unit configuration system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8260990A JPH03280764A (en) 1990-03-29 1990-03-29 Plural-unit configuration system

Publications (1)

Publication Number Publication Date
JPH03280764A true JPH03280764A (en) 1991-12-11

Family

ID=13779220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8260990A Pending JPH03280764A (en) 1990-03-29 1990-03-29 Plural-unit configuration system

Country Status (1)

Country Link
JP (1) JPH03280764A (en)

Similar Documents

Publication Publication Date Title
JPH03280764A (en) Plural-unit configuration system
JP3602962B2 (en) Transmission equipment
JP3570334B2 (en) System switching device
JPS59188244A (en) System switching method
JPS60217445A (en) Communication controller switching system
JP2002252632A (en) Switching method of atm transmission apparatus and its stand-by transmission system
JPH01123545A (en) Communication method for redundant host system in LAN
JPH0514323A (en) Line control device
JPS62269537A (en) Packet switch system switching method
JPH04342332A (en) Transmission system path switching control system
JPH02190050A (en) Polling control system by hdlc-nrm protocol
JPS6015181B2 (en) Exchange control system backup method
JPH06103100A (en) Control switching method for redundant control system
JPS5935242A (en) Switching control system
JPH04304737A (en) Fail safe method for multiplex transmission method
JPS61194939A (en) Communication controller
JPH03235546A (en) Data communication system
JPH0419582B2 (en)
JPH04343538A (en) Data processor
JPH04333162A (en) System switching system
JPS6058745A (en) Data transmission equipment
JPS62141A (en) Line changeover device
JPS62281649A (en) Transfer system for packet information
JPS6223652A (en) Data transmission system
JPS63151155A (en) Fault detection system for space-division switch