JPH03280791A - Picture in picture system - Google Patents
Picture in picture systemInfo
- Publication number
- JPH03280791A JPH03280791A JP8272690A JP8272690A JPH03280791A JP H03280791 A JPH03280791 A JP H03280791A JP 8272690 A JP8272690 A JP 8272690A JP 8272690 A JP8272690 A JP 8272690A JP H03280791 A JPH03280791 A JP H03280791A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- picture
- screen
- child
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- Studio Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はピクチャー・イン・ピクチャー・システムに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to picture-in-picture systems.
ＴＶ、ＶＴＲ，ＶＤＰ等の民生用画像機器では、一方の
画像の一部に縮小したもう一方の画像を挿入して複数の
異なった画像を同時に表示するピクチャー・イン・ピク
チャー・システムが用いられている。In consumer imaging devices such as TVs, VTRs, and VDPs, a picture-in-picture system is used that displays multiple different images at the same time by inserting a reduced image into a portion of one image. There is.
従来、この種のピクチャー・イン・ピクチャー・システ
ムは、第２図に示すように、親画面用映像信号１０を処
理するビデオクロマ処理回路１と同期信号処理回路２、
子画面用映像信号１１を処理するビデオクロマ処理回路
５と同期信号処理回路４、それらの信号１６，１７．１
８を入力する子画面生成回路６および復調した親信号１
２と圧縮した子画面信号１９、親子切換信号２０とを入
力するＲＧＢ信号切替回路８とを有１〜でいる。Conventionally, this type of picture-in-picture system, as shown in FIG. 2, includes a video chroma processing circuit 1 that processes a main screen video signal 10, a synchronization signal processing circuit 2,
Video chroma processing circuit 5 and synchronization signal processing circuit 4 that process the child screen video signal 11, and their signals 16, 17.1
8 and the demodulated main signal 1
2 and an RGB signal switching circuit 8 which inputs the compressed child screen signal 19 and the parent/child switching signal 20.
ビデオクロマ処理回路５により復調された子画面信号１
−８は、子画面生成回路６により圧縮処理をした後、Ｒ
ＧＢ信号切替回路８ （、、ｍより子画面表示期間だけ
親、画面信号と切り替わ・ってＣＲＴ ９へ出力される
。Small screen signal 1 demodulated by video chroma processing circuit 5
-8 is R after being compressed by the child screen generation circuit 6.
The GB signal switching circuit 8 (,, m switches to the parent screen signal only during the child screen display period and outputs it to the CRT 9.
−に述した従来のピクチャー・イン・ピクチャー ・シ
ステムは、子画面の表示期間中は常４．：′親画面にか
わって子画面を表示するため、例えば′丁Ｖの空チヤン
ネル受信時のように、子画面信号が無信号であってもノ
イズあるいは黒だりの画面が表示され、子画面の表示期
間中親画面をかくずことが無駄であるど同時に見苦しい
という欠点があった。- The conventional picture-in-picture system described in 4. :' Because the sub screen is displayed instead of the main screen, even if there is no sub screen signal, such as when receiving an empty channel of 'Ding V, a noise or a black screen will be displayed, and the screen of the sub screen will be Hiding the main screen during the display period is not only wasteful but also unsightly.
本発明のピクチャー・イン・ピクチャー・システムは、
親画面用の映像信号と子画面用の映像信号をそれぞり、
入力するビデオクロマ処理回路と、前記それぞれのビデ
オクロマ処理回路により復調されたままの親画面信号と
復調された後さらに子画面生成回路により圧縮され子画
面信号とを人力し、かつ前記子画面生成回路の出力する
親子切換信号を入力して表示部の親１画面の一部に子画
面をはめ込み表示するＲ Ｇ Ｂ信号切替回路とを有す
るピクチャー・イン・ピクチャ・−・システ１３にお５
１て、前記子画面用の映像信号を入力しグー・ト信号を
出力する子画面用同期検出回路と、前記親子切換信号の
配線中に挿入され前記ゲート信号により前記親子切換信
号の出力を制御するグー１−回路とを有する子切換制御
部を付加ｌ−で構成されてしする。The picture-in-picture system of the present invention includes:
Separate the video signal for the main screen and the video signal for the sub screen,
Manually inputting the input video chroma processing circuit, the main screen signal demodulated by each video chroma processing circuit, and the demodulated and compressed small screen signal by the small screen generation circuit, and generating the small screen. A picture-in-picture system 13 has an RGB signal switching circuit that inputs a parent-child switching signal output from the circuit and displays a child screen by fitting it into a part of the main screen of the display unit.
1, a synchronization detection circuit for a child screen which inputs the video signal for the child screen and outputs a goo-to signal; and a synchronization detection circuit for the child screen which is inserted into the wiring of the parent-child switching signal and controls the output of the parent-child switching signal by the gate signal. A child switching control section having a 1-circuit is additionally constructed.
次に、本発明について図面を参照Ｉ７て説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すプロ・ツク図で・ある
。FIG. 1 is a block diagram showing one embodiment of the present invention.
ピクチャ・−・イン・ピクチャー・システムは、第２図
の子画面用映像信号１１を受（Ｊてゲート・信号１５を
出力する子画面用同期信号検出回路３と、親子切換信号
２０を入力しゲート仏号１−５によりグー１−された親
子切換信号２］を出力するケート回路７とを有する子切
換制御部２３を付加したことが異る煮貝外は従来のピク
チャー・インピクチャー ・システムと同一である。The picture-in-picture system includes a synchronization signal detection circuit 3 for a child screen which receives a video signal 11 for a child screen shown in FIG. The difference is that a child switching control section 23 having a gate circuit 7 that outputs a parent-child switching signal 2 which is turned off by a gate number 1-5 is added. is the same as
次に動作を説明する。親画面用映像信号１０は従来例で
説明したようにビデオクロマ処理回路１により復調され
、コンポーネント信号］２となってＲＧＢ信号切替回路
８へ入力される。Next, the operation will be explained. The main screen video signal 10 is demodulated by the video chroma processing circuit 1 as described in the conventional example, and is input to the RGB signal switching circuit 8 as a component signal]2.
また、同期信号処理回路２では親画面信号１０に同期し
た水平信号３、垂直信号１４を発生しＣＲＴ９へ入力す
る。Further, the synchronizing signal processing circuit 2 generates a horizontal signal 3 and a vertical signal 14 synchronized with the main screen signal 10 and inputs them to the CRT 9.
一方、子画面用映像信号１１は同期信号処理回路４．ビ
デオクロマ処理回路５及び新しく付加された子切換制御
部２３の子画面用同期信号検出回路３へ入力される。On the other hand, the child screen video signal 11 is transmitted to the synchronization signal processing circuit 4. The signal is input to the video chroma processing circuit 5 and the child screen synchronization signal detection circuit 3 of the newly added child switching control section 23.
子画面用同期信号検出回路３では子画面信号１１の有無
を検出し、ゲート信号１５をゲート回路７へ入力する。The child screen synchronization signal detection circuit 3 detects the presence or absence of the child screen signal 11 and inputs a gate signal 15 to the gate circuit 7 .
同期信号処理回路４では従来例と同様に子画面信号】１
に同期１−な水平信号１６．ｌび垂直信号〕−７を発生
し、子画面生成回路６へ入力する。In the synchronization signal processing circuit 4, as in the conventional example, the child screen signal]1
Horizontal signal 16. 1 and vertical signals]-7 and input them to the child screen generation circuit 6.
子画面生成回路ではビデオクロマ処理回路５により復調
された子画面用コンボーネン１へ信号１８を子画面信号
１１に同期１〜で書き込み、圧縮処理した後、親画面信
号１０に同期して子画面信号１つを読み出し、ＲＧ Ｂ
切替回路８へ入力すると共に親子切替信号２０を子切換
制御部２３のゲート・回路７へ入力する４
グー）・回路７ではグー１へ信号１５を受ζつ、子画面
用映像信号１１が入力されている場合はグー１−を開き
、親子切替信号２０をそのまま切替信号２１としてＲＧ
Ｂ信号切替回路８へ入力Ｉ〜、子画面用映像信号１〕が
なくなるとグー１−を閉じ２ゲートされた親子切替信号
２１がＲＧＢ信号切替回路８へ入力されないようにする
。The child screen generation circuit writes the signal 18 to the child screen component 1 demodulated by the video chroma processing circuit 5 to the child screen signal 11 at synchronization 1~, performs compression processing, and then generates the child screen signal in synchronization with the main screen signal 10. Read one, RG B
At the same time, the parent-child switching signal 20 is input to the switching circuit 8, and the parent-child switching signal 20 is input to the gate/circuit 7 of the child switching control section 23. In the circuit 7, the signal 15 is received to the gate 1, and the video signal 11 for the child screen is input. If so, open Goo 1- and use the parent-child switching signal 20 as the switching signal 21 as it is for RG.
When the input I to the B signal switching circuit 8, the small screen video signal 1] is exhausted, the gate 1- is closed to prevent the gated parent-child switching signal 21 from being input to the RGB signal switching circuit 8.
ＲＧ Ｂ信号切替回路８では、グー１−回路７からのゲ
ートされた親子切替信号２１により親画面信号】２と子
画面信号１つとを切り替えてＣＲＴ９へ入力する。In the RG B signal switching circuit 8, the gated parent-child switching signal 21 from the Goo1-circuit 7 switches between the main screen signal 2 and one sub-screen signal and inputs it to the CRT 9.
従って子画面用映像信号１１が無い場合は、ＣＲＴ１９
には親画面のみがうつされる。Therefore, if there is no video signal 11 for the sub-screen, the CRT 19
Only the main screen is transferred.
以上説明したように本発明は、子画面信号が無信号時に
、親子切替信号にゲートをかけ、子画面表示をしないこ
とにより、無信号の子画面を表示するという無駄を省き
見苦しさをなくすことができる効果がある。As explained above, the present invention gates the parent-child switching signal and does not display a sub-screen when there is no sub-screen signal, thereby eliminating the waste and unsightliness of displaying a sub-screen with no signal. It has the effect of
第１図は本発明の一例のブロック図、第２図は従来のピ
クチャー・イン・ピクチャー・システムの一例のブロッ
ク図である。
１・・・ビデオクロマ処理回路、２・・・同期信号処理
回路、３・・・子画面用同期信号検出回路、４・・・同
期信号処理回路、５・・・ビデオクロマ処理回路、６・
・・子画面生成回路、７・・・ゲート回路、８・・・Ｒ
ＧＢ信号切替回路、９・・・ＣＲＴ、１０・・・親画面
用映像信号、１１・・・子画面用映像信号、１２・・・
復調した親画面信号、１３・・・親画面用水平信号、１
４・・・親画面用垂直信号、１５・・・ゲート信号、１
６・・・子画面用水平信号、１７・・・子画面用垂直信
号、１８・・・復調した子画面信号、１９・・・圧縮し
た子画面信号、２０・・・親子切替信号、２１・・・ゲ
ートされた親子切替信号、２２・・・親子画面混合信号
。FIG. 1 is a block diagram of an example of the present invention, and FIG. 2 is a block diagram of an example of a conventional picture-in-picture system. DESCRIPTION OF SYMBOLS 1... Video chroma processing circuit, 2... Synchronization signal processing circuit, 3... Synchronization signal detection circuit for child screen, 4... Synchronization signal processing circuit, 5... Video chroma processing circuit, 6.
...Small screen generation circuit, 7...Gate circuit, 8...R
GB signal switching circuit, 9...CRT, 10...Video signal for main screen, 11...Video signal for sub-screen, 12...
Demodulated main screen signal, 13...Horizontal signal for main screen, 1
4... Vertical signal for main screen, 15... Gate signal, 1
6... Horizontal signal for child screen, 17... Vertical signal for child screen, 18... Demodulated child screen signal, 19... Compressed child screen signal, 20... Parent-child switching signal, 21. ... Gated parent-child switching signal, 22... Parent-child screen mixed signal.
Claims (1)
力するビデオクロマ処理回路と、前記それぞれのビデオ
クロマ処理回路により復調されたままの親画面信号と復
調された後さらに子画面生成回路により圧縮され子画面
信号とを入力し、かつ前記子画面生成回路の出力する親
子切換信号を入力して表示部の親画面の一部に子画面を
はめ込み表示するＲＧＢ信号切替回路とを有するピクチ
ャー・イン・ピクチャー・システムにおいて、前記子画
面用の映像信号を入力しゲート信号を出力する子画面用
同期検出回路と、前記親子切換信号の配線中に挿入され
前記ゲート信号により前記親子切換信号の出力を制御す
るゲート回路とを有する子切換制御部を付加したことを
特徴とするピクチャー・イン・ピクチャー・システム。A video chroma processing circuit that inputs a video signal for the main screen and a video signal for the child screen, and a main screen signal that is demodulated by the respective video chroma processing circuits and then further processed by the child screen generation circuit after being demodulated. and an RGB signal switching circuit that inputs a compressed child screen signal and inputs a parent-child switching signal output from the child screen generation circuit to fit and display the child screen in a part of the main screen of the display unit. In the in-picture system, a synchronization detection circuit for a child screen inputs the video signal for the child screen and outputs a gate signal, and a synchronization detection circuit for the child screen which is inserted into the wiring of the parent child switching signal and outputs the parent child switching signal by the gate signal. 1. A picture-in-picture system further comprising a slave switching control section having a gate circuit for controlling the picture-in-picture system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8272690A JPH03280791A (en) | 1990-03-29 | 1990-03-29 | Picture in picture system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8272690A JPH03280791A (en) | 1990-03-29 | 1990-03-29 | Picture in picture system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03280791A true JPH03280791A (en) | 1991-12-11 |
Family
ID=13782422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8272690A Pending JPH03280791A (en) | 1990-03-29 | 1990-03-29 | Picture in picture system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03280791A (en) |
-
1990
- 1990-03-29 JP JP8272690A patent/JPH03280791A/en active Pending
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