JPH0328097B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to signal transmission using PCM (pulse code modulation), and in particular to differential PCM or PDCM.
The present invention relates to a receiving device used to implement a signal transmission method suitable for (differential PCM).

[Technical Background of the Invention] DPCM is known as an efficient PCM encoding method. While normal PCM encoding transmits values obtained by sampling an analog original signal such as an audio signal every moment as digital data, that is, PCM code, DPCM digitally transmits only the difference from the previous value, that is, the difference between two samples. It is transmitted as data.

Figure 1 shows an example of a transmission system using DPCM encoding.

In the system shown in FIG. 1, the difference is not taken in the form of analog values, but in the form of digital values. That is, an analog original signal, such as an audio signal, is converted into, for example, 15-bit digital data by an A/D (analog-digital) converter 1, and then converted into 15-bit digital data by a delay circuit 2 using a register or the like.
It is applied to the differentiator 3 together with the data delayed by the sample, and the difference data between the two, that is, the DPCM code, is sent to the transmission system in, for example, 16 bits. Here, the term "transmission system" refers to a transmission line such as a simple connection line or a communication line (sometimes using radio waves, light, etc. as a medium) via a modulation/demodulation system, as well as a recording/reproduction system (where the recording medium is the transmission Refers to the so-called transmission system in a broad sense, including the media). In this case transmitted by the transmission system
The 16-bit difference data is added to the previous output of the adder 4 which is delayed by one sample in the delay circuit 5 which is applied to the adder 4, and is accumulated (integrated). ) is applied to the converter 6, and an analog audio signal is output.

A feature of DPCM encoding is that by transmitting differential data between two temporally adjacent samples, the value of transmitted digital data can be reduced on average.

FIG. 2 shows the relationship between the value Dp, which becomes data when the analog original signal So is transmitted by normal PCM, and the value Dd, which becomes data when it is transmitted by DPCM. Ts
is the sampling interval. From the figure, it can be easily understood that as long as the sampling interval Ts is short (appropriate) with respect to the signal period, the transmitted data will have a small value on average. In particular, when the frequency of the analog original signal as shown in the figure is sufficiently lower than the sampling frequency, the difference data Dd has a very small value.

Therefore, for example, when transmitting a certain music signal, the probability of the value of the transmitted digital data tends to become significantly higher as it approaches 0 in the case of DPCM, as shown in FIG. On the other hand, in the case of normal PCM, the tendency to concentrate near 0 is extremely low. It can also be seen from FIG. 3 that the transmitted data value becomes smaller on average in the case of DPCM. In other words, even if it is a 16-bit PCM code, this
If DPCM is used for transmission, most data can normally be transmitted correctly using about 8 to 10 bits, resulting in fairly good transmission.

However, in such DPCM encoding, although the transmitted data value becomes small on average, there is a problem in that the rarely occurring maximum level data has almost the same data value (level) as PCM.

That is, the two characteristics of DPCM are (1) that the average level of transmitted data is very small, and (2) that the maximum level of transmitted data is twice that of ordinary PCM, but the probability of its occurrence is very low.

As a method for effectively transmitting data with a small average level and low probability of occurrence of a high-level signal, normal transmission is performed using a predetermined number of bits that is smaller than the original data, and the range that can be expressed with this predetermined number of bits is It is conceivable that a high-level signal exceeding the above-mentioned value is transmitted by using only the predetermined number of upper effective bits as transmission data and discarding the lower bits. In this case, regarding the lower bits that have been truncated, by transmitting only the truncated number of bits to the receiving side (without sending the contents of the truncated bits), the receiving side can return to the correct number of digits and almost correct reproduction can be performed. In reality, the maximum level value of the samples in the block is detected for each data block consisting of a plurality of samples, and the data in the block is shifted by digits accordingly, and the data of a predetermined number of upper bits is used as the main transmission data. At the same time, the above-mentioned digit shift information is truncated and the main transmission data and scale information are transmitted as scale information corresponding to the number of bits. If you do this,
Almost sufficient information can be transmitted by transmitting one piece of scale information for each data block consisting of a large number of sample data.

A specific example of such a method will be explained in detail. The example described here is for reducing the number of bits of transmitted data using the above method in normal PCM transmission, and the configuration is shown in FIG.

In this case, on the transmitting side, the A/D converter 7 converts an input analog signal, for example, an audio signal, into digital preliminary conversion data of a sufficient number of bits, for example, 15 bits, at predetermined time intervals, and then the digital level detecting means 8 converts the input analog signal into digital preliminary conversion data. The maximum level within the scheduled period or a level approximately equivalent thereto is detected to obtain, for example, 4-bit scale information data, and the digital level variable control means 9 constituting the data compression section adjusts the above A based on the scale information data. The output preliminary conversion data of the /D converter 7 is digitally level-controlled and compressed to obtain, for example, 8-bit main data, and this main data and the scale information data are combined into a large number of main data by the synthesizing means 10. It is sent to the transmission system in such a manner that one piece of scale information data corresponds to the other. On the other hand, on the receiving side, a separation means 11 separates and extracts main data and scale information data from the transmission signal received from the transmission system, and a digital level variable control means 12 constituting a data expansion section converts the main data into the scale information data. Based on this, digital level variable control (data expansion) is performed with control characteristics opposite to those on the transmitting side, and the data is converted into an analog signal by the D/A converter 13 to obtain an output analog signal.

The digital level detection in the digital level detecting means 8 is performed by detecting the number of effective bits in the preliminary conversion data, that is, the most significant bit position of the effective bits excluding the sign bit, and detecting the digital level. The digital level variable control in the variable control means 9 is performed by extracting a bit position portion approximately corresponding to the most significant effective bit position from the preliminary conversion data to create main data.

For example, if the hatched portions of the 15-bit preliminary conversion data are valid bits as shown in Figures 5a to 5c, then in the case of Figure 5a, the valid bits occupy 6 bits of the preliminary conversion data. To obtain 8-bit main data, the lower 8 bits can be used as the main data. At this time, the position where the main data is taken is the lower 8 bits, so this corresponds to extracting only the lower 8 bits from the preliminary conversion data without any bit shifting, and the control level, that is, the scale information at this time, is based on the above shift amount. It becomes "0". As can be seen from this example, the minimum shift amount is 0 bits, so when the effective number of bits is 8 or less, the scale information is uniformly set to "0".
Select. In the case of b in the same figure, the effective number of bits is 9.
Since it is a bit, as is clear from the figure, the extraction position of the main data is shifted to the upper (left) by 1 bit, and the scale information becomes "1", and if 8 bits are taken as the main data, the lowest effective bit, i.e. The LSB (least significant bit) of the preliminary conversion data is ignored, and this part becomes an error. (At this time, it can be considered that the preliminary conversion data is shifted 1 bit lower (to the right) with respect to the extraction position of the 8-bit main data and the lower 1 bit is discarded.)
In this case, the number of effective bits is 15 bits, and the scale information is "7", and in this case, the lower 7 bits of the preliminary conversion data are ignored. That is, in this case, the scale information corresponds to the number of bits to be truncated.
In this way, when the number of effective bits is large, the effective bits ignored and discarded become an error, but the value is sufficiently small compared to the value of the main data. In this case, the maximum level of scale information is 8 (= 2 to the 3rd power)
Since it is a type, the scale information data only needs to be 3 bits. In reality, scale information data corresponds to one data for each large number of preliminary conversion data, so
Scale information is detected and set by measuring or predicting the maximum value in a large number of corresponding preliminary conversion data in advance, and common scale information (shift amount) is set for the corresponding large number of preliminary conversion data, and this scale information is set. Detection and updating are performed for each of the above-mentioned large number of preliminary conversion data.

Note that in the above, the main data consists only of the data extracted from the pre-converted data by bit shifting, but this means that the analog signal handled is a unipolar signal with only one positive or negative signal, and the pre-converted data includes a sign (polarity) bit. or if the code bit is included but does not need to be transmitted. On the other hand, if the input analog signal is a bipolar signal such as an audio signal, in which both positive and negative signals are mixed, the preliminary conversion data itself usually has at least the MSB sign bit or equivalent bit.
This bit is included as the most significant bit (most significant bit) and is also essentially an important effective bit.
Of course, the data can be used as the main data. That is, when the main data is 8 bits, one of the bits is used as a code bit, so the main data is composed of the code bit and 7 bits of data obtained by bit shifting.

By the way, in this case, the digital level variable control means 9 on the receiving side bit-shifts the main data separated from the transmission signal by the shift amount indicated by the similarly separated scale information data to obtain the same number of bits as the preliminary conversion data. You will get playback data. That is, in the case of the example shown in FIG. 5a, 8-bit main data is used as is as the lower 8 bits to obtain 15-bit reproduced data that is equal to the original preliminary conversion data. Similarly, in the example of figure b, 8
The main data of the bit is shifted 1 bit to the upper part (to the left) and 1 bit of additional data is added to the lower part to create 15-bit playback data.In the example shown in Figure c, the 8-bit main data is shifted 7 bits to the upper part and then to the lower part. Add 7 bits of additional data to create 15 bits of playback data. Here, as the data added to the lower order, data uniquely determined in advance, such as 0 data or average value data, is used. That is, suppose, for example, that the 15-bit preliminary conversion data is as shown in FIG. 6a. When transmitting 8-bit main data based on this (here we are considering the case where the sign bit is not considered), the upper 8 effective bits are transmitted as shown in the figure.
The bits are extracted as main data and the lower 4 bits are discarded. The receiving side receives the main data, and bit-shifts the main data according to the scale information corresponding to the bit position from which the 8-bit main data in the preliminary conversion data is extracted, thereby creating 15-bit main data. At this time, basically, as shown in FIG. 6b, 0 data "0000" corresponding to the shifted number of bits is added. In addition, in order to reduce the error from the original data on average, it is necessary to set a value that approximately corresponds to the average value of the data that can be expressed by the number of bits, for example, an average value such as "0111" as shown in Figure 6c. It is effective to use the data as additional data. Even if the additional data is data other than these 0 data or average value data, there is often no practical problem as long as the value is constant for each bit number. It goes without saying that when these additional data take values other than 0 data, the difference between the value indicated by the lower bits of the original data, that is, the preliminary conversion data, and the above additional data is essentially truncated data. .

Incidentally, although the method shown in the example shown in FIG. 4 can be used when transmitting ordinary PCM, that is, PCM code data as is, it is difficult and undesirable to apply it as is to DPCM.

The main reason is as shown in Figure 1.
This is because receiving DPCM requires decoding by accumulating and integrating the received data, and errors caused by truncation on the transmitting side are added up on the receiving side, resulting in a large error.

For this reason, even if the average level of the transmitted data was lowered using DPCM, it was not only impossible to reduce the number of bits of the actual transmitted data, but also the number of bits sometimes increased.

It is also possible to consider lowering the number of transmission bits by setting a certain rule in advance between transmission and reception, such as ADPCM (adaptive DPCM - adaptive differential PCM), and performing non-linear transmission and reception while lowering the level resolution on the receiving side. However, such ADPCM etc. cannot be said to have very high precision and have many problems, such as not only being unable to perform good reproduction on the receiving side but also making the equipment complex.

On the other hand, the following transmission method can be considered as a transmission method that takes advantage of the effect of reducing the average level of transmitted data by DPCM and enables high-precision transmission with a small number of bits.

That is, a first process of successively converting PCM code data into DPCM data, and then testing the size of the DPCM code data based on the DPCM code data and converting a predetermined number of samples into one block within the data block. In order to send the maximum amount of data, the main data (transmission) of the expected number of bits with a data length shorter than the DPCM code data is extracted from sequentially selected bit positions, giving priority to the upper effective bits, and the above bit positions are scaled. A second process for extracting information as information, and if there is lower-order data that was substantially truncated when obtaining the main data, the truncated data is added to the subsequent DPCM code data converted in the first process. Then, in place of the DPCM code data obtained in the first process,
a third process to be subjected to the process;
A fourth process of sending the main data and scale information obtained in the second process to the transmission system as a result of the process, and a process of receiving the transmission data transmitted in this fourth process and based on the received data. Receive main data using bit shift according to reception scale information.
This method performs a fifth process of converting to DPCM data and decoding and demodulating the DPCM code.

By the way, in such a system, in the data compression section which is the center of the second and third processing on the transmitting side, specifically, for example, the accumulator is operated as follows.

In other words, for example, 16-bit input DPCM code data is extracted by extracting the previous sender data.
It is added to the lower residual data (ie, truncated data) remaining in the accumulator without being transmitted, and the upper effective bit portion, for example 8 bits, of the data after this addition is extracted and transmitted as main data. As a result, the lower residual data remains in the accumulator again. Here, the bit position (upper effective bit position) from which the main data is extracted is the same within the same data block, and information indicating this bit position is transmitted as a scale value for each block.

In this case, the input DPCM code data is added to the lower residual data in the accumulator, resulting in a carry exceeding the transmission bit range of the main data.
It may overflow. input
The number of effective digits of the DPCM code data is checked in advance for each block before addition in the accumulator, and the difference between the maximum value in the block and the number of digits of the main transmission data is the scale value (≧0). So,
When the above-mentioned overflow occurs, the most important upper bit among the valid bits is not transmitted, resulting in a large error.

Referring to FIG. 7, an example will be described in which 2's complement is used for the DPCM code and the scale value is constant at 6.

Due to the previous main data extraction, the lower residual data remaining in the accumulator is "110000" as shown in Figure 7a, and the DPCM code data of "0001111111011101" as shown in Figure 7b is input. In this case, the two are added in the accumulator, and data "0010000000001101" is obtained as shown in c of the figure. Since the scale value is 6, the main transmission data in this case is "10000000" as shown in d of the figure. In this case, in the original data, the most significant sign bit becomes "1", which indicates negative, instead of "0", which indicates positive, due to the above-mentioned carry, even though the data is positive.
It would be a big mistake.

In order for this kind of inconvenience to occur, a) there must be seven or more consecutive “1”s in positive input data, and b) the content of the accumulator (i.e., the previous lower residual data) and the lower Two conditions must be met: the result of addition with the digit must carry beyond the transmission bit position from which the transmission main data is extracted. Therefore, although the probability of its occurrence is generally as low as about 2 to the 9th power = 1 in 512, it is not desirable.

If the scale value is significantly lower than the previous data block, an overflow similar to that described above may occur, and the probability of this type of overflow occurring becomes extremely high.

The occurrence of this type of overflow will be described in detail with reference to FIG. In this case, the DPCM code is still 2's complement, and the scale value changes from 6 to 1.

When the lower residual data remaining in the accumulator due to the previous main data extraction is "110000" as shown in Figure 8a, the scale value changes from 6 to 1, and at the same time as "110000" as shown in Figure 8b. When input data ``0000000011011101'' is given, the two are added in the accumulator to obtain data ``0000000100001101'' as shown in c of the figure. Since the scale value is "1", the main transmission data in this case is "10000110" as shown in Figure d, and the most significant sign bit is also "1" which means negative due to carry. I get used to it.

The probability of such a case occurring is generally very high, approximately 2 to the 4th power = 1 in 16, and it becomes a big problem.

As described above, the occurrence of errors when performing data compression as described above poses a serious problem in practice.

[Object of the Invention] The object of the present invention is to transmit PCM encoded data with a small number of bits and with high precision, effectively reducing the probability of occurrence of overflow errors in the transmitted data, and further increasing the transmission precision. An object of the present invention is to provide a receiving device used to implement a signal transmission method to obtain a signal.

[Summary of the Invention] The present invention solves the overflow error by setting only the first data of the data block as the transmission main data to a larger number of bits than other data and transmitting the upper bits extra. It is characterized by preventing its occurrence.

[Embodiments of the invention] First, the principle of the present invention will be explained.

As mentioned above, overflow to the transmitted main data occurs most often when the scale value changes in the direction of decreasing the absolute value of the data. That is, this is when the state changes from transmitting the upper order of the original data (preliminary conversion data) to transmitting the lower order as the main transmission data. In such a case, it can no longer be said that the data content remaining in the above-mentioned accumulator is sufficiently smaller than the transmitted data, and the probability that an overflow will occur when the two are added becomes extremely high. However, what should be noted here is that the probability of overflow occurring is always the first data in a data block, whereas the probability of overflow occurring is usually very low for the second and subsequent data in the data block. The point is that there is nothing more than that.

Therefore, in the signal transmission system according to an embodiment of the present invention, only the first transmission main data of each data block is transmitted with a bit length that is, for example, one bit larger than the other transmission main data.

For example, the bit length of the main transmission data is basically 8.
In the case where the data block is composed of bits, only the first transmission main data of the data block is transmitted using 9 bits. If an overflow occurs in the transmitted data due to the addition of the lower residual data remaining in the accumulator and the new (subsequent) original data, as in the case of Fig. 8 explained earlier, this is transmitted in 8 bits. For example, in the case of 2's complement, etc., the more positive the value becomes, the bigger the error will be.
On the other hand, in this method, only the beginning of the data block is transmitted as 9 bits, 1 bit more than the first bit, so even though 8 bits is positive data, it is sent as a negative value such as "10000110" due to overflow. The data is also correctly transmitted as "010000110" with "0" indicating positive added to the beginning of the data.

In this way, if the transmission bit length of the first transmission main data of a block is made longer than the other transmission main data, the other data (not the beginning of the block) may have a shorter bit length. This is a feature of this method.

Here, the reason why it is necessary to increase the bit length of only the first transmission main data will be explained in detail with reference to FIG. 9, which shows a specific example.

Assume that the data remaining in the accumulator as a result of the accumulation of the lower residual data is "011001" as shown in FIG. 9a. At this time, the scale value is 6. Here, when DPCM code data "0001101001010010" which is the original data is given as shown in FIG. 5B, both are added to obtain data "0001101001101011" as shown in FIG. At this time, the scale value is still 6, so d
Data “01101001” shown in is transmitted as main data. Therefore, the data "101011" shown in e of the figure remains in the accumulator. Suppose that the data block ends in this state, and the data "0000000011011010" shown in figure f is given at the beginning of the next data block, and at the same time the scale value changes to 1. In this case, the result added by the accumulator is "0000000100000101" as shown in figure g, and if 8-bit data is extracted as the main transmission data,
“10000010” becomes the main transmission data, and in 2′s complement etc., the polarity is reversed and a big error occurs, but in this method, 9 is used as the main transmission data.
Since bit data is extracted and transmitted, "010000010" shown in h in the figure becomes the main data to be transmitted. Since the scale value is 1, the data "1" shown in i in the figure remains in the accumulator as lower residual data.

In this way, when the scale value suddenly decreases from 6 to 1, the previous contents of the accumulator (Fig. 9e) will be changed to the original data given (Fig.
The addition result (FIG. 9g) overflows from the predetermined scale value 1, since it is not sufficiently small compared to FIG. 9f). Therefore, if 8-bit main data is extracted and transmitted according to a given scale value of 1 (leave 1 bit in the accumulator and take out the upper 8 bits), the most significant bit of the transmitted main data will be "1". Although this results in negative data, such errors can be effectively prevented by setting the transmitted main data to 9 bits. In other words, if only the first block is 9 bits, then the number of digits in the accumulator will be one digit corresponding to the scale value, and the data in the accumulator will be sufficiently small compared to the main data to be transmitted, so overflow will occur. almost no longer occurs.
If the probability of overflow occurrence is reduced in this way, countermeasures can be taken by various means not shown here.

The increase in transmission amount in this case is
Since it only increases by 1 bit per block, it is extremely small.

For example, when one block consists of 32 samples, the amount of data transmitted for one block is 8 bits x 32 + 3 bits (scale information) = 259 bits when this method is not applied, and in this method, 1 The bit increases to 260 bits. Therefore,
The rate of increase in transmission amount is less than 0.4% per block, so there is virtually no problem.

In the above, we have explained the case where the scale value changes from 6 to 1. However, in the same case as above, if the maximum change in the scale value in the data decreasing direction is larger than this, the first It becomes necessary to increase the amount of data bit length larger than the above.

For example, when the scale value changes from 6 to 0, the first transmission main data of the block must be 10 bits, two bits more than the other transmission main data. In other words, as shown in Figure 10, 8-bit data is extracted from the 16-bit original data with a scale value of 6 and transmitted.The maximum amount of data left in the accumulator at the end of the block is 8 bits, and this data is transferred to the next block. When the data is added to the first original data of the block and a carry occurs, the polarity information of the 2's complement appears above the 10th bit from the LSB. Therefore, if the scale value becomes 0 in this state, the polarity information cannot be sent unless the transmission main data is set to 10 bits.

In this way, the increase in the number of transmission bits of the first main data of a block may be 2 bits or 3 bits. However, this value is determined by the number of bits of the original data and the transmitted main data, and therefore, depending on the design, the increase can be limited to 1 bit, or it can be set to a value of 2 bits or more. You can also do it.

In addition, although the above description deals with the case where the original data is transmitted as DPCM encoded data 2′s complement, the same applies to cases where the code of the original data is a normal binary code or other codes. It will never change.

Note that although the above explanation was given as simply increasing the number of bits of the first transmitted main data of a data block, overflow occurs when the scale value decreases, that is, when the absolute value of the original data is scaled in the direction of decreasing. Since the value changes most of the time, the increase in the number of bits of the transmission main data may be controlled depending on the direction of change of the scale value.

In other words, basically, it is possible to obtain a sufficient effect in practice simply by increasing the number of bits of the initial transmission main data for all data blocks, but in this case, by including a considerable increase in the number of transmission bits that is originally unnecessary, , which may be unfavorable in terms of transmission efficiency. Therefore, when the scale value changes in a direction where overflow is less likely to occur, it is possible to limit the increase in the number of transmission bits and set the amount of increase in the number of transmission bits to 0 or to a smaller value than in other cases, resulting in more efficient data transmission. becomes possible.

Next, an embodiment of the present invention showing a specific implementation mode of such a system will be described. In this embodiment, the amount of increase in transmission bits related to the direction of change in the scale value described above is controlled, and the number of transmission bits is increased only when the scale value changes in the direction in which the absolute value of data decreases. I try to do this.

FIG. 11 shows the configuration of the transmitting side according to this embodiment, and FIG. 12 shows the configuration of the receiving device according to this embodiment.

In FIG. 11, the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

That is, 1 is an A/D converter that converts an analog original signal input such as an audio signal into digital data, 2 is a sample delay circuit that delays A/D converted PCM code data by one sample, and 3 is a sample delay circuit that delays A/D converted PCM code data by one sample.
This is a subtractor that takes the difference between two consecutive samples of PCM code data, and the output of the subtractor 3 is, for example,
16-bit DPCM code data is obtained. 14
is a block delay circuit constructed using, for example, a memory, and delays the DPCM code data output from the subtractor 3 by one data block. 15
is a scale determination circuit that detects the maximum absolute value of the sample data in each data block from all the data for one block of DPCM code data output from the subtractor 3, and calculates the block based on the detected value. The set scale value is output as 4-bit data, including when no digit shift is required.

Note that the above is based on the case where the 2's complement, which exists on the positive and negative sides of the sign, is used, and the scale value is determined by the maximum absolute value of the sample data, but it is assumed that the scale value is determined by the maximum absolute value of the sample data. In some cases, it may be necessary to detect the scale value using another method suitable for the sign.

16 is an accumulator section, and 17 is a data compression circuit, both of which realize the functions of the data compression section described above.

In other words, the accumulator unit 16 is a portion substantially equivalent to the above-mentioned accumulator itself, and includes, for example, a 16-bit full adder and an 8-bit hold register. Then, of the output of the full adder, the lower several bits corresponding to the scale value given from the scale determining circuit 15, that is, the lower residual data equivalent are held. The full adder is given from the block delay circuit 14.
The DPCM code data and the previous lower residual data held in the hold register are added. The addition result of this full adder is directly applied to the data compression circuit 17. The data compression circuit 17 is a part for extracting compressed data, and is a part for extracting compressed data.
The function is to extract the data of the expected number of bits at the bit position corresponding to the scale value given from the scale determination circuit 15 from the 16-bit data given from the full adder No. 6, and to detect the change in the scale value and determine the scale value. It has a function of increasing the expected number of bits (number of bits for data extraction) for the first data of the block on the upper digit side only when the number changes in the decreasing direction. That is, in this case, the data compression circuit 17 basically extracts 8-bit data from the output of the full adder and uses it as the main transmission data.
When the scale value decreases, the number of bits of only the first data of the block is increased toward the upper side, for example, 9.
In other cases, the above-mentioned 8 bits are extracted and output as transmission main data.

This 8- or 9-bit transmission main data and 4-bit scale information data for each block output from the scale determining circuit 15 are supplied to the transmitting circuit 18, where both data are converted from parallel data to serial data and time-divided. are multiplexed and sent serially to the transmission system.

Further, 19 is a control sequencer section, which includes the above-mentioned sections, namely the A/D converter 1, the sample delay circuit 2, the difference unit 3, the block delay circuit 14,
scale determination circuit 15, accumulator section 16,
In order to operate each part of the data compression circuit 17 and the transmission circuit 18 in a predetermined manner at a predetermined timing, control signals are given to each part. In addition,
When a decrease in the scale value is detected in the data compression circuit 17, a signal to that effect is input from the data compression circuit 17 to the control sequencer section 19, and the signal is transmitted from the control sequencer section 19 to the transmission circuit 18. A control command corresponding to a 1-bit increase in main data is given.

The above is the configuration of the transmitting side according to this embodiment, and next, the configuration of the receiving device according to this embodiment will be explained.

In FIG. 12, 20 separates 8 or 9-bit main data and 4-bit scale information data from the transmission signal input from the transmission system, and converts both data from serial data to parallel data. This is a receiving circuit for
This receiving circuit 20 has a function of detecting that the scale value has changed in a decreasing direction and sending a signal to that effect to a control sequencer section 27 to be described later.
It also has a function of controlling the number of bits for separating main data to be transmitted in response to the control signal sent back from the control sequencer section 27 in response to the change in the number of bits when the scale value changes as described above. .

Reference numeral 21 denotes a shift clock generator, which outputs a shift clock corresponding to the number of bits to be shifted based on the scale information data input from the receiving circuit 20. 22 is a data decompression circuit using, for example, a shift register, which in this case heavy-shifts the main data input from the receiving circuit 20, that is, compressed DPCM code data (8 bits), using a shift clock provided from a shift clock generator 21. Expands to bit DPCM received data. In addition, if this data expansion is designed so that the entire operation is performed with a 2's complement code, the polarity code in the MSB of the main data (compressed DPCM code) is The same values (0 or 1) as in the shift register are processed so that they are consecutively located at the upper position of the shift register. That is, in this data decompression circuit 22, the 8-bit main data is subjected to a bit shift according to the scale information of the block to which the data belongs, and is converted into DPCM reception data. In this case, 23 is an adder circuit consisting of a 16-bit full adder, which corresponds to adder 4 in FIG. Output as . Reference numeral 24 denotes a data hold register, which roughly corresponds to the delay circuit 5 in FIG. and the latest data decompression circuit output (DPCM received data). A D/A converter 25 substantially corresponds to the D/A converter 6 in FIG. 1, and returns the 15-bit PCM received data held in the data hold register 24 to an analog value. 26 is a low pass filter that removes unnecessary high frequency components from the output of the D/A converter 25, and an analog signal such as an audio signal is obtained as the output of this filter.

Reference numeral 27 denotes a control sequencer section, which operates each of the above-mentioned sections, such as the receiving circuit 20, shift clock generating section 21, data decompression circuit 22, data hold register 24, etc. in a predetermined manner at a predetermined timing. It provides a control signal and also controls the number of bits when the above-mentioned receiving circuit 20 separates the main data.

Next, the operation in the above-described configuration will be explained.

First, on the transmitting side, an analog original signal (for example, an audio signal) is converted to PCM code data (15 bits) by an A/D converter 1, and the difference between the data and the previous sample, which is delayed by a sample delay circuit 2, is called the difference. It is calculated by the unit 3 and converted into DPCM code data (16 bits).

This data is given to the scale determining circuit 15, and it is divided into one block consisting of a certain number of samples.
The maximum difference (to be more precise, the absolute value of the difference, i.e. the value with the largest difference, as differences have positive and negative values) is calculated from the DPCM code data, and the scale value (digit shift information) data (4 bit) is output from this scale determining circuit 15.

The set scale value output of this scale determination circuit 15 is updated for each block, and
This is scale value data common to DPCM code data. In order to correct this time lag in scale information detection, the DPCM code data delayed by one block in the block delay circuit 14 is transferred to the accumulator section 1.
6 and a data compression circuit 17, the data is sequentially compressed according to the scale value. That is, in the accumulator section 16, the contents of the hold register holding the lower residual data and the block delay circuit 1
The DPCM code data output from 4 is added by full adder, and the lower residual data equivalent of this addition result (that is, the data of the lower several bits corresponding to the scale value) is held in the hold register and used for the next DPCM. Used for addition with code data. The addition result of the full adder is directly applied to the data compression circuit 17. The data compression circuit 17 detects a change in the scale value given from the scale determination circuit 15, and when the scale value changes in a decreasing direction from the 16-bit data given from the accumulator section 16 (full adder), the block is The number of bits is 9 bits in the first case and 8 bits in other cases, and the bit position according to the above scale value (in this case, the position corresponding to the LSB of the data to be extracted is used as the reference).
data is extracted.

This essentially means that the DPCM code data output from the block delay circuit 14 described above is converted to the upper effective bits according to the scale value output from the scale determination circuit 15 by 8 bits in the normal case, and the scale value is decreased. For only the first data when the direction changes, 1 bit is added to the upper bit, 9 bits are extracted and output as main data, and when the lower bits are truncated, the truncated (lower residual) data is left. This corresponds to adding the data to the next DPCM encoded data and subjecting it to similar data compression and truncated data addition processing. For this reason, the lower residual data of the truncated digits that were not transmitted in the main data are added to and accumulated with the next DPCM code data, so that they are substantially included in the subsequent main data. This main data and scale information data are sent to the transmission system via the transmission circuit 18. It goes without saying that in order to insert scale information data during time-division synthesis in the transmitting circuit 18, processing such as time-axis compression of the main data string may be performed as necessary.

While PCM transmits values that include the sign from a reference level, such as 0 level, DPCM transmits the difference between samples, so if the frequency of an audio signal is very high compared to the sampling period, the The difference between around the peak value and around the negative peak value may be the DPCM code, and for this reason
The maximum number of bits for DPCM code data is 1 bit more than that for PCM code data. Therefore, in the above example, there are nine scale values for obtaining 16-bit DPCM code data from 15-bit PCM code data and transmitting it as 8- and 9-bit main data, including cases where digit shifting is not required. The scale data is 4 bits.

The operation of the receiving device that receives the transmission data sent to the transmission system in this manner will be described.

The transmission signal provided from the transmission system is composed of 8- and 9-bit main data consisting of compressed DPCM codes serialized and time-division multiplexed, and 4-bit scale information data for each data block. The receiving circuit 20 to which this transmission signal is applied separates scale information data and main data from the received signal, parallelizes these data, and outputs the parallel data.
Specifically, by the cooperative operation of the receiving circuit 20 and the control sequencer unit 27, for example, scale information for each block (for example, based on synchronization data added as necessary) is first separated and extracted from the received signal. From this, a change in the scale value in the decreasing direction is detected. When this change in the decreasing direction is detected, 9 bits are used as the first data of the block following the scale information data, otherwise, 8 bits each are used as main data for the period of that block, that is, the next scale. Information is extracted sequentially until it is separated and extracted. These reception main data and reception scale information data are input from the reception circuit 20 to the data expansion circuit 22 and shift clock generation section 21, respectively. A shift clock corresponding to the received scale information data is output from the shift clock generating section 21, and this shift clock is applied to the data expansion circuit 22 to perform a digit shift (bit shift) to the 8-bit received main data.
is applied, and in the case of a 2's complement code, the upper bits are filled with polarity bits and converted to 16-bit DPCM received data. At this time, 0 data, for example, is added to the lower blank bits generated by the digit shift. This DPCM reception data is given to the adder circuit 23, and is added to the output data of the adder circuit 23 of one sample before, which is held in the data hold register 24. That is, the output data of this addition circuit 23 is the cumulative (integrated) value of the DPCM received data, that is, 15-bit PCM received data. This PCM reception data is sequentially D/A converted by a D/A converter 25 via a data hold register 24, and unnecessary high frequency components are removed by a low pass filter 26, and the data is output as an analog signal of, for example, an audio signal.

In this way, the transmitting side can receive the transmitted data in which the truncated part, that is, the digit loss part is accumulated and reflected in the subsequent transmitted data, and perform effective decoding and demodulation, so that the 8-bit main data can be Just by receiving the data, the accuracy equivalent to reception with 9 bits or more can be achieved.

As mentioned above, it is possible to extremely effectively prevent the occurrence of overflow due to fluctuations in scale values during data compression on the transmitting side, effectively realizing high-efficiency PCM that can be transmitted using a small number of bits. can do.

Although not specifically explained above, if the probability of overflow occurrence becomes low, measures can be taken to substantially eliminate the influence of overflow, such as correcting or correcting the obtained data using various methods. Is possible.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, but can be implemented with various modifications without changing the gist thereof.

For example, the functions of the part consisting of the accumulator unit 16 and the data compression circuit 17 can be replaced by other configurations, such as detecting carry information to the transmission main data by cumulative addition of the zero-digit part, and detecting carry information from the original data (preliminary conversion data). The extraction of transmission data may be performed in parallel in different parts. The point is to increase the number of transmission bits only for the first transmission main data of a block to prevent overflow and to perform transmission.

Further, part or all of the digital processing functions described above may be realized using a computer.

Furthermore, the scale information is set by reversing the standard of the bit position for main data extraction (based on the upper 8 digits), setting scale information ``7'' in Figure 5a, ``6'' in Figure 5B, and ``6'' in Figure 5C. It is also possible to perform binary encoding by setting the value to "0".

Note that when the present invention is used to transmit stereo audio signals, various techniques used in ordinary digital audio technology, such as time division multiplexing by alternately transmitting the transmission data of both left and right channels, can be used. Of course, it is also possible to use them together.

[Effects of the Invention] According to the present invention, DPCM encoded data can be transmitted with high accuracy using a small number of bits, and in addition, the occurrence of overflow errors during data compression can be effectively prevented, and error compensation can be easily performed. It is possible to provide a receiving device used to implement a signal transmission method that can further improve accuracy.

[Brief explanation of drawings]

Figure 1 is a system block diagram to explain an example of DPCM, and Figures 2 and 3 are typical system block diagrams.
Diagram 4 to explain the difference between PCM and DPCM
The figure is a system block diagram showing an example of data compression in PCM, Figures 5 and 6 are diagrams for explaining the same example, and Figures 7 and 8 are diagrams for explaining the occurrence of an overflow error in the same example. FIG. 9 is a diagram for explaining the principle of the signal transmission method according to the present invention. FIG. 10 is a diagram for explaining the increase in the number of bits of main data transmitted in the same method. FIG. 12 is a block diagram showing the configuration of a transmitting side according to an embodiment of the present invention. FIG. 12 is a block diagram showing the configuration of a receiving apparatus according to an embodiment of the present invention. 1... A/D converter, 2... Sample delay circuit, 3
...Differentiator, 14...Block delay circuit, 15...Scale determination circuit, 16...Accumulator section, 17...
Data compression circuit, 18... Transmission circuit, 20... Receiving circuit, 21... Shift clock generating section, 22... Data expansion circuit, 23... Adding circuit, 24... Data hold register, 25... D/A converter, 26... Low pass filter.

Claims (1)

[Claims] 1. The first data of the data block is selected from the bit position corresponding to the scale value based on the maximum value in each block selected in the data block unit consisting of data groups for each scheduled time of the DPCM code original data. For only the data, the number of bits is set to be larger than other data so that the number of bits is higher than that of other data, and the planned number of bits is sequentially extracted, and the lower residual data is cumulatively added to the subsequent original data.
In a receiving device that obtains main data having a smaller number of bits than the original data from the original data and receives a transmission signal including scale information indicating the scale value and the main data, the received main data is divided into each data block. a data importing means for importing only the first data with a predetermined number of bits each having a larger number of bits than other data; and a data decompression means for decompressing the received main data taken in by this means in accordance with reception scale information. , and decoding and demodulating means for decoding and demodulating the expanded data obtained by this means. 2. The receiving device according to claim 1, wherein the decoding and demodulating means includes means for performing integral processing on the decompressed data. 3 From the bit position corresponding to the scale value based on the maximum value within each block selected for each data block consisting of data groups for each scheduled time of the DPCM code original data, the scale value changes in the direction of decreasing the absolute value of the data. For only the first data of the data block mentioned above, the number of bits is set to be larger than that of other data, and the data with the planned number of bits is extracted sequentially, and the lower residual data is cumulatively extracted. In a receiving device that obtains main data having a smaller number of bits than the original data from the original data by adding it to subsequent original data, and receives a transmission signal including scale information indicating the scale value and the main data. , scale change determination means for determining the direction of change in the scale value from received scale information; a data importing means for importing data with a larger number of bits than other data, and in other cases, taking in the same number of bits as the other data uniformly within the data block, each with a predetermined number of bits; A receiving device characterized by comprising: data expansion means for expanding the received main reception data in accordance with reception scale information; and decoding and demodulation means for decoding and demodulating the expanded data obtained by this means. . 4. The receiving apparatus according to claim 3, wherein the decoding and demodulating means includes means for performing integral processing on the decompressed data.