JPH0328728U - - Google Patents

Info

Publication number
JPH0328728U
JPH0328728U JP1989089717U JP8971789U JPH0328728U JP H0328728 U JPH0328728 U JP H0328728U JP 1989089717 U JP1989089717 U JP 1989089717U JP 8971789 U JP8971789 U JP 8971789U JP H0328728 U JPH0328728 U JP H0328728U
Authority
JP
Japan
Prior art keywords
main surface
circuit board
outer periphery
semiconductor element
electrode provided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989089717U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989089717U priority Critical patent/JPH0328728U/ja
Publication of JPH0328728U publication Critical patent/JPH0328728U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/701—Tape-automated bond [TAB] connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例の半導体装置の平面
図、第２図は第１図の断面図、第３図は従来の半
導体装置の一例の平面図、第４図は第３図の断面
図、第５図は従来の半導体装置の他例の平面図、
第６図は第５図の断面図である。 １，１１，２１……半導体素子、２ａ，２ｂ，
１２ａ，１２ｂ，２２ａ，２２ｂ，６，１６，２
６……電極、３，１３，２３……回路基板、４，
２４，７，１７……導体パターン、５ａ，５ｂ，
２５ａ，２５ｂ，２５ｃ……リード、８，１８…
…導電線。 FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of FIG. 1, FIG. 3 is a plan view of an example of a conventional semiconductor device, and FIG. A sectional view, FIG. 5 is a plan view of another example of a conventional semiconductor device,
FIG. 6 is a sectional view of FIG. 5. 1, 11, 21... semiconductor element, 2a, 2b,
12a, 12b, 22a, 22b, 6, 16, 2
6... Electrode, 3, 13, 23... Circuit board, 4,
24, 7, 17... conductor pattern, 5a, 5b,
25a, 25b, 25c...Lead, 8, 18...
...conductive wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子の主表面上の一外周部に設けられた
電極と回路基板の一主面から延びたリードとが接
続され、前記半導体素子の他の外周部に設けられ
た電極と前記回路基板の他主面上の導電パターン
とが導電線で接続されていることを特徴とする半
導体装置。 An electrode provided on one outer periphery of the main surface of the semiconductor element is connected to a lead extending from one main surface of the circuit board, and an electrode provided on the other outer periphery of the semiconductor element and the other lead of the circuit board are connected. A semiconductor device characterized in that a conductive pattern on a main surface is connected with a conductive wire.
JP1989089717U 1989-07-28 1989-07-28 Pending JPH0328728U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989089717U JPH0328728U (en) 1989-07-28 1989-07-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989089717U JPH0328728U (en) 1989-07-28 1989-07-28

Publications (1)

Publication Number Publication Date
JPH0328728U true JPH0328728U (en) 1991-03-22

Family

ID=31639286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989089717U Pending JPH0328728U (en) 1989-07-28 1989-07-28

Country Status (1)

Country Link
JP (1) JPH0328728U (en)

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