JPH0328834U - - Google Patents

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Publication number
JPH0328834U
JPH0328834U JP8842789U JP8842789U JPH0328834U JP H0328834 U JPH0328834 U JP H0328834U JP 8842789 U JP8842789 U JP 8842789U JP 8842789 U JP8842789 U JP 8842789U JP H0328834 U JPH0328834 U JP H0328834U
Authority
JP
Japan
Prior art keywords
frequency
signal
control signal
circuit
variable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8842789U
Other languages
Japanese (ja)
Other versions
JP2520762Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989088427U priority Critical patent/JP2520762Y2/en
Publication of JPH0328834U publication Critical patent/JPH0328834U/ja
Application granted granted Critical
Publication of JP2520762Y2 publication Critical patent/JP2520762Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロツク図、
第2図は本考案の他の実施例を示すブロツク図、
第3図、第4図はPLL回路の従来構成を示すブ
ロツク図である。 10……VCO、11……周波数設定回路、1
2……位相比較回路、15……基準信号発振器、
17……ループフイルタ、18……比較回路、2
2……制限回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing another embodiment of the present invention;
FIGS. 3 and 4 are block diagrams showing the conventional structure of a PLL circuit. 10...VCO, 11...Frequency setting circuit, 1
2... Phase comparison circuit, 15... Reference signal oscillator,
17...Loop filter, 18...Comparison circuit, 2
2...Limiting circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 外部からの信号に応じて出力信号の周波数
が可変される周波数可変発振器と、 前記周波数可変発振器からの出力信号の周波数
を、基準周波数の整数倍に当たる所望の周波数に
ほぼ等しくなるように設定する周波数設定手段と
、 前記周波数可変発振器からの出力信号を前記基
準周波数の基準信号によつてサンプリングし、基
準周波数の高調波成分との位相差を検出し、検出
信号を出力するミキサ型の位相比較回路と、 前記周波数可変発振器からの出力信号の周波数
を前記所望の周波数に一致させる方向へ制御する
ための制御信号を前記検出信号より得て該制御信
号を前記周波数可変発振器へ出力するループフイ
ルタと、 前記制御信号の大きさが、予め設定された限度
範囲を越えたことを検出する比較回路と、 前記比較回路からの検出信号を受け、前記制御
信号の大きさを所定時間だけ前記限度範囲内に入
るように制限する制限回路とを備えたことを特徴
とするPLL回路。 (2) 前記周波数設定手段は、前記周波数可変発
振器の周波数を、前記基準周波数の整数倍から基
準周波数より低い所定周波数だけ離間した所望の
周波数にほぼ等しくなるように設定し、前記位相
比較回路からの検出信号と前記所定周波数の信号
との位相差を第2の位相比較器で検出し、該第2
の位相比較器の検出信号から前記ループフイルタ
により制御信号を得るようにした第1項記載のP
LL回路。 (3) 前記制限回路が、前記周波数設定手段から
の周波数切換信号を受け、前記制御信号の大きさ
を所定時間だけ限度範囲内に入いるように制限る
すようにした第1項または第2項記載のPLL回
路。
[Claims for Utility Model Registration] (1) A variable frequency oscillator whose output signal frequency is varied according to an external signal; and a desired frequency variable oscillator whose output signal frequency is an integral multiple of a reference frequency sampling the output signal from the variable frequency oscillator using the reference signal of the reference frequency and detecting a phase difference with a harmonic component of the reference frequency; a mixer-type phase comparator circuit that outputs a detection signal, and a control signal for controlling the frequency of the output signal from the variable frequency oscillator in a direction to match the desired frequency, from the detection signal, and converting the control signal into the control signal. a loop filter that outputs to the variable frequency oscillator; a comparison circuit that detects that the magnitude of the control signal exceeds a preset limit range; and a comparison circuit that receives the detection signal from the comparison circuit and compares the control signal with A PLL circuit comprising: a limiting circuit that limits the size to within the limit range for a predetermined period of time. (2) The frequency setting means sets the frequency of the variable frequency oscillator to be approximately equal to a desired frequency spaced from an integral multiple of the reference frequency by a predetermined frequency lower than the reference frequency, and A second phase comparator detects the phase difference between the detection signal and the signal of the predetermined frequency, and the second
P according to item 1, wherein the control signal is obtained by the loop filter from the detection signal of the phase comparator.
LL circuit. (3) Clause 1 or 2, wherein the limiting circuit receives a frequency switching signal from the frequency setting means and limits the magnitude of the control signal to be within a limit range for a predetermined time. PLL circuit described in section.
JP1989088427U 1989-07-27 1989-07-27 PLL circuit Expired - Lifetime JP2520762Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989088427U JP2520762Y2 (en) 1989-07-27 1989-07-27 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989088427U JP2520762Y2 (en) 1989-07-27 1989-07-27 PLL circuit

Publications (2)

Publication Number Publication Date
JPH0328834U true JPH0328834U (en) 1991-03-22
JP2520762Y2 JP2520762Y2 (en) 1996-12-18

Family

ID=31638044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989088427U Expired - Lifetime JP2520762Y2 (en) 1989-07-27 1989-07-27 PLL circuit

Country Status (1)

Country Link
JP (1) JP2520762Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009151820A (en) * 1999-02-22 2009-07-09 Microsoft Corp Dual axis articulated computer input device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843044U (en) * 1981-09-18 1983-03-23 株式会社東芝 frequency synthesizer
JPS5843043U (en) * 1981-09-18 1983-03-23 株式会社東芝 frequency synthesizer
JPS62188427A (en) * 1986-02-13 1987-08-18 Yokogawa Electric Corp Signal generation circuit
JPS63200619A (en) * 1987-02-16 1988-08-18 Nec Corp Phase locked oscillator
JPS63173928U (en) * 1987-04-30 1988-11-11
JPS63312724A (en) * 1987-06-16 1988-12-21 Nec Corp Frequency synthesizer
JPS6489621A (en) * 1987-09-30 1989-04-04 Nec Corp Frequency synthesizer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843044U (en) * 1981-09-18 1983-03-23 株式会社東芝 frequency synthesizer
JPS5843043U (en) * 1981-09-18 1983-03-23 株式会社東芝 frequency synthesizer
JPS62188427A (en) * 1986-02-13 1987-08-18 Yokogawa Electric Corp Signal generation circuit
JPS63200619A (en) * 1987-02-16 1988-08-18 Nec Corp Phase locked oscillator
JPS63173928U (en) * 1987-04-30 1988-11-11
JPS63312724A (en) * 1987-06-16 1988-12-21 Nec Corp Frequency synthesizer
JPS6489621A (en) * 1987-09-30 1989-04-04 Nec Corp Frequency synthesizer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009151820A (en) * 1999-02-22 2009-07-09 Microsoft Corp Dual axis articulated computer input device

Also Published As

Publication number Publication date
JP2520762Y2 (en) 1996-12-18

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