JPH03292076A - Still picture reproducing device - Google Patents

Abstract

PURPOSE:To simplify the device and to reduce the cost by allowing 1st and 2nd interpolation circuits of two systems to apply inter-frame interpolation to a luminance signal processing system and a chrominance signal processing system and using a 3rd interpolation circuit so as to apply inter-field interpolation thereby applying reproduction of a still picture of a MUSE video signal. CONSTITUTION:Signals S5, S6 are fed to low pass filters 41, 42 applying band limit of 12MHz in the luminance signal processing and the signal of 32MHz rate is converted into a signal of 24MHz rate by clock converters 43, 44 and signals S7, S8 are obtained. The output signals S7, S8 from the two systems of low pass filters 41, 42 and the clock converters 43, 44 are subject to inter-field interpolation by an interpolation circuit 45 according to an inter-field subsample phase and a still picture S9 of a luminance signal is reproduced. On the other hand, the chrominance signal processing does not require low pass filters and clock converters different from the luminance signal processing. Output signals S5, S6 of interpolation circuits 37, 38 are interpolated by an interpolation circuit 46 according to an inter-field subsample phase for a chrominance signal to reproduce the still picture S10 for the chrominance signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a still image reproducing device, and specifically relates to a MUS
The present invention relates to a still image reproducing device that performs still image reproducing processing of a video signal in the E transmission system.

High-definition television is being developed as the next generation of television, and regular experimental broadcasts via satellite have begun. The core of high-definition technology is the MUSE system (Multiple Sub-Nyquist-S).
This is a band compression technology that enables satellite broadcasting, called the Amplifying Encoding method. This has 1125 scan lines, 608 Z field frequency, and 22 bands.
MHz RGB 3 channel signal band 8.1MHz
, which compresses the band into a single channel signal.

The background art of the present invention is a still image reproduction method in the decoding process of the band-compressed MUSE signal.

[Conventional technology]

The MUSE signal is a signal 3 with a band of 22 MHz each for RC and B.
The encoder and decoder are first briefly explained with reference to FIG. 4, which compresses the band of a channel signal into a single channel signal of 8.1 MHz. In the same figure,
1 is an encoder on the transmitting side in high-definition broadcasting, 2
is the receiving side decoder. The encoder 1 is a combination of a still image compression processing circuit 3 that performs still image compression processing, a video compression processing circuit 4 that performs video compression processing, a motion detection circuit 5 that detects a moving area of an image, and a motion detection circuit 5. It is composed of a mixer 6 that mixes still images and moving images based on the ratio. Note that motion detection is to detect a moving area of an image, and this is performed based on the amount of change in the image over time, that is, the difference between images.

In the MtJSE method, the band compression method is different for still images and moving images. Since still images do not change over time, Figure 5 (a)
) shows the luminance signal, and FIG. 5(b) shows the color signal.
Divide the image into 4 fields (field offset subsample, frame/line offset subsample)
and transmit one picture. On the other hand, since a moving image is completed in one field and is compressed and transmitted, the picture is rougher than a still image.

Then, the motion detection circuit 5 detects the amount of motion for each pixel, and generates a MUSE signal while changing the mixing ratio of still images and moving images. The above is the basic operation of the MUSE encoder 1.

The MUSE decoder 2 includes a still image playback processing circuit 7 that performs still image playback processing, a video playback processing circuit 8 that performs video playback processing, a motion detection circuit 9 that detects a moving area of an image from the MUSE signal, and a motion detection circuit. The mixer 10 performs mixing for reproduction of still images and moving images 1 based on the mixing ratio from 9. The MUSE decoder 2 performs the opposite process to that of the encoder 1. Since the moving image reproduces the picture only within the current field, no field memory is required.

In order to reproduce one still image, information for four fields is required, and memory for three fields is required. That is, this is because information up to three fields before the current field is required. Also, motion detection is 4
Requires memory for one field. This is MUSE
This is because in the signal, the method of thinning out pixels to be transmitted changes for each field, and the period is four fields.

Therefore, in order to determine whether the pixel is moving or stationary, information from four fields before, which transmitted the pixel at the same position, is required.

In this way, the decoder detects the amount of movement for each pixel and creates a picture by changing the mixing ratio of still images and moving images. The above is the basic operation of the MUSE decoder 2.

Next, the conventional configuration of the still image playback system on the decoder side is
Shown as shown. In the figure, 11 and 12 are frame memories (memory for two fields), 13 is a subtracter, 14 is an interpolation circuit that performs interpolation between frames, and 15 is an interpolation circuit that performs interpolation between fields. The circuit 16 is a one field memory. In still image playback processing, interframe interpolation is first performed using frame memories 11 and 12 for motion detection, and the current field picture S 1 (Z-Ov) and 2 are
F) Picture S that is a composite of the previous picture S2 [Z″2v]
3 (Z-Ov ten Z-2V).

Thereafter, by passing it through the field memory 16 and delaying it by one field time, a signal S4 (corresponding to picture S4) niha (Z-1" + Z"V) is output. By combining this signal S4 and picture S3 (Z-Ov+Z-'') (interpolation between fields), a still image (Z-OV+z-I
v+Z4v+z−v] is output.

[Problem to be solved by the invention]

However, in such a conventional still image reproducing device, picture S 3 (Z-0V+Z-") to picture S
4 (Z-" + Z-"), the configuration required one field memory 16, which resulted in the problem of complicating the memory peripheral circuit, leading to a more complex decoder configuration and higher costs. There was a point.

In other words, the MUSE signal is originally transmitted at 16 MHz, and the 1 field memory 16 for 2 frames is 16 MHz old.
It works. However, picture s3 (z-0v+Z-ZV
), the signal between frames is interpolated, so the operating clock is 32M1 (double z.
Processing unique to the E method, in particular, converting the clock rate of the luminance signal to a 24MH2 signal is performed. Since field delay processing is performed after this processing, the operating clock of the luminance system memory becomes 24 Mtlz, which becomes a factor in complicating the memory peripheral circuit.

In addition, this field delay processing requires a large amount of memory, 3 Mbit in the luminance signal processing section and IMbit in the color signal processing section (the above is a rough estimate), which is the largest memory among all the memories used in the MUSE decoder. occupies a large proportion.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a still image reproducing apparatus that can simplify the configuration of a decoder and reduce costs by eliminating the field memory after interframe interpolation.

[Means to solve the problem]

In order to achieve the above object, the still image reproducing device according to the present invention has the following features:
As the principle diagram is shown in FIG. 1, there is a storage means 21 that divides the MUSE signal into 4 fields and stores 2 frames, and a 2-system first system that interpolates between frames using the signal from the storage means 21. .2 interpolation circuits 22 and 23, and the first
．． A third interpolation circuit 24 performs interpolation between fields using the signals from the interpolation circuits 22 and 23 of the second system, and both the luminance signal processing system and the color signal processing system The interpolation circuits 22 and 23 perform interpolation between frames, and the third interpolation circuit 24 performs interpolation between fields to reproduce still images of the MUSE video signal. In addition, in this principle diagram, the storage means 21 has four 1
It has field memories 25-28.

Further, 29 is a subtracter from which a difference between four fields (two frames) is outputted and a motion detection signal is extracted.

[Effect]

In the first place, a motion detection circuit is essential to the MUSE decoder. For this purpose, a memory for two frames (four fields) is absolutely necessary to detect the amount of change between two frames (transmitting the same pixel). Therefore, in the present invention, when playing a still image, the two
The memory for the frame, that is, the four one-field memories 25 to 28 in the storage means 21 is used, and
By having two interframe interpolation systems, the above problem can be solved.

That is, in the present invention, interpolation between frames is performed in the two systems of the first and second interpolation circuits 22 and 23 for both the luminance signal processing system and the color signal processing system, and the third interpolation circuit 2
4, interpolation between fields is performed and a still image of the MUSE video signal is reproduced.

Therefore, it is possible to eliminate field delay memories with different operating clocks for interfield interpolation in both the luminance signal processing system and the chrominance signal processing system, simplifying the configuration of the MtJSE decoder and reducing cost.

〔Example〕

The present invention will be described below with reference to the drawings; FIG. 2 is a diagram showing an embodiment of a still image reproducing apparatus according to the present invention.

FIG. 2 is a block diagram of this device, and in this figure,
Reference numeral 31 denotes a storage means corresponding to a 2-frame memory for motion detection, and is composed of four 1-field memories 32 to 35. This configuration is adopted because the amount of change between two frames for motion detection is, in other words, the amount of conversion between four fields. 36 is a subtracter that outputs the difference between 4 fields (2 frames) and extracts a motion detection signal;
37.38 is an interpolation circuit (1.2) that performs interframe interpolation.
39 is a brightness processing circuit, and 40 is a color processing circuit.

The brightness processing circuit 39 includes a low pass filter (LPF) 41.
42, clock converters 43 and 44, and an interpolation circuit (corresponding to a third interpolation circuit) 45 that performs interfield interpolation for luminance, and a color processing circuit 40 that performs interfield interpolation for color. Interpolation circuit (equivalent to the third interpolation circuit)
It has 46. Low-pass filters 41 and 42 each have a 1 value for output signals S5 and S6 of interpolation circuits 37 and 38.
2MHz band limit and clock converter 43.44
is the output of the low-pass filter 41.42 32MI (
z rate signals to 24 MHz rate signals. The interpolation circuit 45 reproduces the luminance still image based on the output signals from the clock converters 43 and 44. Further, the interpolation circuit 46 reproduces a color still image based on the output signals of the interpolation circuits 37 and 38.

Note that 81 to SIO are signals corresponding to pictures.

In the above configuration, in still image reproduction processing, the current field S1 and the signal S3 two fields before are interpolated by the interpolation circuit 37 according to the current interframe subsample phase, and at the same time, the signals S2 and S3 two fields before are interpolated by the interpolation circuit 37. The interpolation circuit 38 interpolates the signal S4 before the field according to the interframe subsample phase of the previous field. However, the brightness and color can be changed.

In the luminance signal processing, the signals S5 and S6 are passed through low-pass filters 41 and 42 that limit the band to 12 MHz, and then
Clock converters 43 and 44 convert the 32 MHz rate signals into 24 MHz rate signals to obtain signals S7 and S8. These low-pass filters 41, 42 and clock converters 43, 44 are a unique method of still image processing of luminance signals in the MUSE system.

The output signals S7 and S8 from the two systems of low-pass filters 41 and 42 and the clock converters 43 and 44 are sent to the interpolation circuit 4.
5, interpolation between fields is performed according to the interfield subsample phase, and a still image S9 of the luminance signal is reproduced.

On the other hand, chrominance signal processing does not require a low-pass filter or clock converter unlike luminance signal processing. Interpolation circuit 37.38
By interpolating the output signals S5 and S6 by the interpolation circuit 46 according to the interfield subsample phase for the color signal, a still image SIO of the color signal is reproduced.

In this way, in this embodiment, the memory for still image playback is replaced with the memory for motion detection (four 1-field memories 32 to 35).
), the still image system (1
It is now possible to delete field memories with different operating clocks that were independently available (for both colors at once). As a result, field delay memories with different operating clocks for interfield interpolation can be removed from both the luminance signal processing system and the chrominance signal processing system, making it possible to simplify the configuration of the MUSE decoder and reduce costs. can.

Next, FIG. 3 is a diagram showing another embodiment of the present invention, in which the configuration of the brightness processing circuit 51 is different.

That is, the luminance processing circuit 51 is not provided with an independent clock converter, but is provided with a clock conversion/interpolation circuit (which simultaneously performs clock conversion and interfield interpolation of the luminance signal) after the two low-pass filters 41 and 42. 52 (corresponding to the third interpolation circuit) is arranged. Therefore, the two 32MHz rate signals output from the low-pass filters 41 and 42 are converted to 48MHz by the clock conversion/interpolation circuit 52.
It is output as a signal S9 that has undergone interfield interpolation at a Hz rate. In particular, the process of clock conversion is 24MH
Converting to 2 rates can be realized by almost the same processing, and has the advantage that the circuit scale can be further reduced than in the above implementation.

〔Effect of the invention〕

According to the present invention, the field memory after interframe interpolation can be deleted, and the configuration of the MUSE decoder can be simplified and costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the present invention. FIG. 2 is a block diagram showing one embodiment of the still image reproducing device according to the present invention. FIG. 3 is a diagram illustrating another embodiment of the still image reproducing device according to the present invention. 4 to 6 are diagrams showing a conventional still image reproducing device, FIG. 4 is a diagram showing the configuration of the MUSE encoder/decoder, and FIG. 5 is a diagram explaining the MUSE pixel transmission method. , FIG. 6 is a diagram showing the configuration of the still image reproduction system. 21.31...Storage means, 22.23...1.2 interpolation circuit, 24...
...Third interpolation circuit, 25-28.32-35...1 field memory, 29.36...Subtractor, 37.38...Inside Insertion circuit (No. 1.39.51.
...Brightness processing circuit, 40...Color processing circuit, 4L 42...Low pass filter, 43.44
. . . Clock converter, 45 . . . Interpolation circuit (third interpolation circuit), 46 . . . Interpolation circuit (third interpolation circuit), 52. ...Clock conversion/interpolation circuit (third interpolation circuit). 2 interpolation circuit)

Claims (1)

[Claims] Storage means for dividing the MUSE signal into four fields and storing two frames; and two for interpolating between frames using the signal from the storage means.
The system includes first and second interpolation circuits of the system, and a third interpolation circuit that performs interpolation between fields using signals from the first and second interpolation circuits, and includes a luminance signal processing system and a color signal processing system. In both systems, the first and second interpolation circuits of the two systems perform interpolation between frames, and the third interpolation circuit performs interpolation between fields to reproduce still images of the MUSE video signal. A still image reproducing device characterized by being configured as follows.