JPH03292770A - Electrostatic induction thyristor - Google Patents

Abstract

PURPOSE:To simplify a drive circuit and a control circuit and to reduce the drive circuit in number of component parts by a method wherein a MOS diode on a gate and an insulated gate transistor formed between a gate and a cathode or a gate and an anode are integrated on the same chip. CONSTITUTION:A gate electrode 25 formed on a p<+> region 31 through the intermediary of a gate insulating film 26 not only constitutes a MOS diode but also serves as the gate electrode of an insulated gate transistor which makes p<+> regions 31 and 32 serve as its source and drain respectively. A normally-on type MOSFET is connected between the gate and the cathode of an Si thyristor. The relation between the impurity concentration of an n-region 22 and a distance between a pair of the p<+> regions 31 is so set as to enable a depletion layer to pinch off a channel when a voltage is not applied to the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a novel structure of an electrostatic induction thyristor (hereinafter referred to as SI thyristor). In particular, insulation control (MOS-Control) can simplify the gate drive circuit.
ed) Regarding the structure of SI thyristors.

[Prior art]

The SI thyristor is a latching amplifier type switch element, and has conventionally been driven by inputting positive and negative trigger pulses and quench pulses to the gate. An example is shown in FIG.

In FIG. 1(a), a p-channel MOS transistor 52
and a buffer 7 consisting of a positive bias power supply 54, an n-channel MOSI transistor 53, and a negative bias power supply 55.
Trigger pulse φON and quench pulse φ are applied to the circuit. ,,
It works by inputting each. Tri force pulse φ
and quench pulse φ. , , are input at the timing shown in (b). Furthermore, in order to limit the current flowing into the gate of the SI thyristor, a resistor 57 is inserted between the buffer 1 circuit and the gate of the SI thyristor. Capacitor 56 is a speed-up capacitor. Diode 58 is provided so that the current from the gate during turn-off is not limited by resistor 57. As described above, there are conventional problems such as the complexity of the control circuit that generates the trigger pulse and the quench pulse, and the large number of parts for the buffer 1. 2, a driving method as shown in FIG.

In FIG. 2(a), 1 is a normally-off type SI transistor, a capacitor 2 is connected to its gate, and a P-channel MOS transistor 31 is connected between the gate and the cathode. The gate of this MOS transistor is controlled by a pulse φ6, which serves as an input pulse to the capacitor 2. The waveform of pulse φ6 is shown in (bl).

In FIG. 2(b), during the period T1, the pulse φ6 is ■. At a potential If, this potential causes the MOSI transistor 3 to
The SI thyristor 1 is in a conductive state, and the SI thyristor 1 is in a cut-off state with the gate and cathode being at the same T position. At time t1, pulse φ.

or V. ff to V. When it changes to n, SI thyristor 1
The potential of the gate increases due to capacitive coupling. At this time, the V of pulse φ6. At a potential of 0, the MOS transistor 31 is in a cutoff state.

A normally-off SI thyristor transitions from a cut-off state to a conduction state when a small voltage corresponding to the diffusion potential of the gate and cathode is applied. At this time, gate current other than that necessary to charge the input capacitance seen from the gate is not required, and there is no need to flow direct current.

During the period T2, the SI thyristor 1 is in a conductive state.

Pulse φ at time t2. or V. 0 to V. When it changes to ff, the MOS transistor becomes conductive again and the SI thyristor 1 becomes cut off. However, Fig. 2 (
Conventionally, there has been no proposal regarding a specific structure for integrating the MOS transistors shown in a) on the same chip.

Basically, compared to a conventional thyristor consisting of a p+npn+ four-layer structure, an SI thyristor, in which the forward current of a p"n-n+ or p"nin" diode is controlled by a control electrode, is particularly effective at its operating speed. Excellent.SI
Since the conduction and cutoff of the current in the thyristor is performed by controlling the potential barrier g+ generated in the channel,
As already pointed out, the control electrode of the SI thyristor is not limited to the junction type, but may also be of the insulated gate type.
It has been proposed in Japanese Patent Publication No. 21275, Japanese Patent Publication No. 62-21276, Japanese Patent Publication No. 61-48790, etc. The cross-sectional structure of this example is shown in FIG. In FIG. 3, the n+ region 23 is a cathode region, the P+ region 21 is an anode region, and 26 is an insulating film.The thin part of the side wall of the cut recess becomes the gate insulating film, and a positive voltage is applied to the gate electrode 25. By doing this, a channel is formed directly under the gate insulating film, the potential barrier in front of the cathode is removed, and the SI thyristor is turned on. The cathode electrode 23' is in ohmic contact with both the n+ region 23 and the P+ region 24, and most of the holes flowing from the anode flow into the P+ region 24.

Turn-off is realized by applying a negative voltage to the gate electrode 25. If the P+ region 24 is not shared with the cathode region, but an independent electrode is formed, and holes are drawn out from the P+ region 24 during turn-off, turn-off can be achieved faster, but the gate drive circuit becomes complicated. In any case.

In the conventionally proposed insulated gate SI thyristors, no specific structure for connecting the MO3I transistor between the gate and cathode and integrating them on the same chip is shown.

[Purpose of the invention]

An object of the present invention is to provide a novel structure of an insulation control (MO3 control) SI thyristor that can simplify the drive circuit/control circuit and reduce the number of parts in the drive circuit.

Another object of the present invention is to provide a novel structure that can reduce gate loss without sacrificing the inherent characteristics of an SI thyristor, such as low forward voltage drop and high switching speed. Yet another object of the invention is to
The object of the present invention is to provide a concrete structure for integrating a gate driving MOS diode and a MOS transistor on the same chip.

[Summary of the invention]

In this FIBA, there is a MOS diode above the gate, and an insulated gate transistor (MOS transistor, M
It is characterized by being an SI thyristor integrated on the same chip. The Mine invention will be explained in detail using FIG. 4. Figure 4(a) is a plan view;
FIG. 4b) is a sectional view taken along line A-A' in FIG. 4(a).

P+ region 21 is an anode region, n- region 22 is a region forming a channel, n+ region 23 is a cathode region, P+
Region 32 is an auxiliary cathode region.

P+ region 31 is a gate region. 23' is a cathode electrode, and 21' is an anode electrode. Reference numeral 25 denotes a gate electrode, which is connected to the M
While constituting an OS diode, it also serves as the gate electrode of an insulated gate transistor in which the P+ region 31 is the source and the P+ region 32 is the drain. In FIG. 4(b), a normally-on type (depletion type) P-channel MOSFET is connected between the gate and cathode of the SI thyristor.

The relationship between the impurity density of the n- region 22 and the distance between the pair of P+ regions 31 is selected such that the depletion layer extending from the P+ region pinches off the channel when no voltage is applied to the gate electrode 25. The SI thyristor is of the normally-off type.The operation in this configuration is similar to that described in FIG. Gate potential or V. When ff" is 0 volts, the SI thyristor shown in FIG. 4 having the P+ region 31 as its gate is in a cut-off state, and the P-channel MOSFET having the P+ region 31 as a source and the P+ region 32 as a drain is in a conductive state.

V with a positive gate potential. When the voltage changes to 0, the potential of the P+ region 31 rises due to capacitive coupling, and the potential barrier to electrons formed on the front surface of the n+ cathode region 23 lowers, and electrons are injected from the cathode region 23. The injected electrons are accumulated near the interface between the D region 22 and the p+ anode region 21, and the potential barrier to holes on the anode side disappears, causing hole injection from the anode, which in turn inhibits the injection of electrons from the cathode. Further promote S
Icyrisk turns on. At this time P channel M
O8FET enters the cut-off state. V on the gate electrode. When ff is applied, the P-channel MOSFET becomes conductive, and holes are extracted to the cathode side through the P+ region 31, and the potential barrier to electrons on the front surface of the cathode becomes high.
I thyristor turns off.

〔Example〕

It goes without saying that the structure of the present invention is not limited to that shown in FIG. Although FIG. 4 shows only one unit, that is, one channel surrounded by a pair of gate regions 31, for large current applications, a multi-channel structure in which many of these units are connected in parallel, a gate electrode and a cathode electrode, etc. Of course, a structure in which they are interdigitated with each other may be used. FIG. 5 shows an example of an interdigital structure, in which, like FIG. 4, 23' or the cathode electrode,
25 is the gate electrode.

Fig. 5(a) is a plan view, Fig. 5(b) is a sectional view taken along the x-x' force direction in Fig. 5(a), and Fig. 5(c) is a Y
FIG. 3 is a cross-sectional view taken along the -Y' direction. Unlike FIG. 4, the P+ region 32 of the auxiliary cathode region is formed in contact with the n+ cathode region 23 along the longitudinal direction of the cathode, that is, the Y-Y' direction. In Figure 5, the fourth
Similarly to the figure, a P channel insulated gate °-transistor is constructed in which the p+ gate region 31 is used as a source region, the auxiliary cathode region 32 is used as a drain region, and the gate electrode 25 of the SI thyristor is used as a gate electrode. In FIG. 4, since the auxiliary cathode region 32 or the cathode region 23 are formed on both sides, there is a drawback that the margin for mask alignment is reduced.
In the illustrated example, since the auxiliary cathode region Vj, 32 is formed along the longitudinal direction of the cathode region 23, the same level of mask alignment margin as the conventional Sl-thyristor is required, and manufacturing is easy. The p region 21 is an anode region, and 21 is an anode electrode. . 25' Beam 1 - This is the bonding pad part for taking out the gate electrode for taking out the wire.It is made of metal C such as A2. The gate electrode 25 is made of polycrystalline silicon or W, 'v10, Ti, Ta.
, high melting point metal such as Nb, or WS1□, MoS
It may be a silicide such as i2, or it may be a composite film in which silicide is formed on other crystalline silicon as the F base. The impurity density in the n-region is 10~ioT
4 cm-3, the impurity density of the P+ region 21.31.322 may be 10-10" cm-6, and the impurity density of the n+ region 10-10"cm-'; in this case,
If the interval between the p gate regions 31 is set to 6 μm or less, a normally-off Sl thyristor is obtained. cathode n
Assuming that the diffusion width of the region 23 is 2 μm, the diffusion width of the auxiliary cathode region 32 is 1 μm, and the width of the overlap portion between the cathode n region 23 and the auxiliary cathode region 32 is 0.5 μm, as shown in FIG. 4(b). In the structure, the insulated gate transistor connected between the gate and cathode has a channel length of 1
．． MO8SIT on the 5μ surface roared. MO8SIT is MOS
The on-resistance R6N is smaller than that of the FET, which is preferable. Fifth
In the structure shown in Figure (C), the diffusion width of the auxiliary cathode is 3μ.
m, the channel length of MO8SIT is 1.5 μm.

In this case, the width of the overlap part between the auxiliary cathode and the cathode can be selected as necessary, for example, 10μ-
That's fine. S [Gate current when thyristor turns off■
The current flows through the insulated gate transistor between the cathode and the cathode, but
If the on-resistance ROM of the insulated gate transistor is large, the voltage drop due to T(roH-R, . . . ) becomes larger than the gate potential V of the Sl thyristor in the ON state, and the Sl thyristor becomes yX(ω lean-off. Therefore, R. If RoN is large, the maximum gate current flowing at turn-off (f” l
(:y8(7X) becomes small, which increases the time required for turn-off, which is not preferable.

In order to further reduce the on-resistance R0N of MO8SIT, it is best to use a structure as shown in FIG. 6 to reduce the channel length and widen the channel width. In Figure 6, the gate spacing of the 8-tooth cyrisk is 6 μm, and the cathode n+
The region diffusion width is 2 μm.4 The width of the auxiliary cathode region 32 is 2 μm, and the distance between the P+ region 31 and the auxiliary cathode region 32 is 0.
MO8SIT with 5μm or channel length 0.5μm
FIG. 6(a) is a plan view, and FIG. 6(b) is a sectional view taken along the x-x' force direction. In FIG. 6, an SI anode short structure is used in which the P+ anode region 21 is divided and an n+ short region 41 is inserted between them. Transfer electrons to P+ anode and n+
Due to the potential during the short, the n+ short part 41
By sweeping the current to 1, the Tilmi flow at the time of turn-off of the Sl thyristor becomes smaller, and higher-speed switching becomes possible. The pitch of the P+ anode is 2 times the electron diffusion length.
Choose less than double.

FIG. 7 shows an example in which the auxiliary cathode region 32 is formed inside the cathode region 23. 33 is a 9-layer or i-layer, and is designed to be almost completely depleted. P+ area 32
MO3S is applied to the part of the cathode region 23 between the region 33 and the region 33.
The structure is such that an IT intrinsic gate void is formed and the potential barrier there is controlled by the potential of the gate electrode 25. In FIG. 7, the P+ region 32 becomes the source region of MO8SIT, and the P+ region 31 becomes the drain region. The area of the cathode region can be increased compared to that shown in FIG.

Can flow large current. In Fig. 7, as in Fig. 6,
- Does it have a tonoiodine structure?

Further, an n-buffer layer 42 is formed near the anode region. The impurity density of the n buffer layer 42 is lX1015
~1×1017C1rL-3, n-region 22.23
The impurity density of I Q” −l Q13ci ” (7
) By making the impurity density extremely low, the electric field strength between the gate and the anode is uniform, and the depletion layer from the gate does not reach the anode, which increases the maximum forward blocking voltage and increases the switching speed. It is also fast, and the voltage drop during conduction can be reduced. If the maximum forward blocking voltage is the same as when there is no n-buffer 1 layer 42, the thickness of the n-region 22 can be halved, and naturally the forward voltage drop will be small and the switching speed will be faster.

FIG. 8 is an example of an SI thyristor with a cut gate structure. To be more specific, the first gate has a notched gate structure.
This is an example of a double gate SI thyristor in which the second gate has a surface gate structure.

In FIG. 8(a), the n+ region 23 is a cathode region, the P+ region 32 is an auxiliary cathode region, and the P+ region 21 is an anode region, which are the same as those shown in FIGS. 4 to 7, but P+ The region 31 is the first gate region, the n+ region 42 is the second gate region, and the electrode 25 formed in the cut recess.
is the first gate electrode, 51 is the second gate electrode, n+ region 4
3 is an auxiliary anode area. A P-channel insulated gate transistor having the P+ region 31 as the source region and the P+ region 32 as the drain region, or an n-channel insulating transistor formed between the cathode and the first gate, with the N+ region 42 as the source region and the N+ region 43 as the drain region. The gate transistor is connected between the second gate and the anode, and if expressed as an equal circuit, it will be as shown in FIG. 8(b).

The impurity density of the n- region 22 is adjusted such that the depletion layer extending from the P+ region 31 of the first gate completely depletes the n- region 22 of the notch convex portion in a state where no voltage is applied to the first gate electrode 25; Select the width of the notch protrusion. An n channel is formed in the n- region 22 in contact with the double gate insulating film 26 shown in FIG. This is done by applying a potential, lowering the potential barrier to holes in front of the 7-node through capacitive coupling, and injecting holes from the anode. Turn-off is at the 1st gate KM
, the second gate electrodes are both set to zero potential, and P on the first gate side is set to zero potential.
Turning on the channel insulated gate transistor and extracting the hole through the first gate region 31;
This is done by turning on the n-channel insulated gate transistor on the gate side and drawing electrons out through the second gate region 42 to raise the potential barrier in front of the cathode and in front of the seventh node. In this case, unlike a single-gate SI thyristor, there is no Tilmi flow due to residual electrons, and high-speed switching of sub-microseconds or less can be easily performed. Of course, it is also possible to use a notched gate type ngle gate SI thyristor, which does not have the structure on the second gate side in FIG. Conversely, it is also possible to omit the structure of the first whistle gate and drive the second gate. Further, it is also possible to make the first gate a surface gate and the second gate a cut gate structure, or the first gate,
Of course, both the second gate and the second gate may have a cut gate structure. Furthermore, only one of the first gate and the second gate may be controlled to be insulated, and the other may be a double-gate SI thyristor driven by a normal junction gate.

FIG. 9 shows an insulation-controlled single-gate SI thyristor that is driven only on the second gate side, and can also be thought of as an inverted-operation SI thyristor with an anode pump. When combined with an SI thyristor with cathode top that operates in an upright position, it becomes a complementary configuration and can be used as a bidirectional switch. 9th
In the figure, P+ region 21 is an anode region, n+ region 23 is a cathode region, and n+ region 42 is a gate region. The n+ region 43 is the auxiliary anode region, the drain region of the n-channel insulated gate transistor, and the n+ region 42 is the source region. The operation is based on the n formed in front of the p″ anode region.
Turn-on and turn-off are performed by controlling the potential barrier created by the + gate region. That is, the gate electrode 5
1, a negative potential is applied to capacitive coupling to lower the potential barrier in front of the P+ anode region, and holes are injected from the p+ anode region and accumulated near the interface between the n− region 22 and the n″′ region 23, and the n+ Electrons are injected from the cathode region 23,
The injected electrons further lower the potential barrier in front of the P+ anode region, and the inverted SI thyristor is turned on. Turn-off is performed by setting the gate electrode to O volts, turning on the n-channel insulated gate transistor, and drawing out electrons through the n+ region 42, thereby increasing the potential barrier in front of the p+ anode region.

FIG. 10 shows yet another embodiment of the present invention, which improves the drawbacks of the embodiment shown in FIG. 4, such as a small mask alignment margin.

That is, in the embodiment shown in FIG. 4(b), a P channel M
In order to form an OS transistor, fine dimensions are required, and the widths of the P+ region 32 and the n+ cathode region 23 cannot be made large, resulting in problems such as the inability to flow a large current, and There is a problem that leakage current easily flows, and there is also a problem that once the spacing between the n+ region 23 and the P+ region 31 is determined, the design margin of the P channel MOS transistor is restricted. These problems are solved in Fig. 10, and Fig. 10(a) is a plan view, and Fig. 10(b) is a sectional view along the Y-Y' direction of Fig. 10(a). It has a channel structure. Although not shown, the cross-sectional view along the X-Y′ direction in FIG. 10(a) is exactly the same as FIG. 5(b), and n
The voltage barrier between the cathode and the anode is controlled by the potential barrier formed by the p+ gate region 31 which narrows the cathode region. In FIG. 10, one P-channel MOS transistor is connected to each unit in the longitudinal direction of the cathode, and the structure can be considered as a further development of FIG. 5. In FIG. 5, the p+ gate regions are separated for each unit, but in FIG. 10, they are all continuously formed as one unit. In FIG. 10, the P+ auxiliary cathode region 32 is a drain region, the P+ region 31 is a source region,
A MOS transistor having 25 as a gate electrode is formed.

Unlike FIGS. 4 and 5, in FIG. 10 the P+ region 3 corresponds to the gate length of the P channel MOS transistor.
2 and the P+ region 31 can be freely selected regardless of the structure and dimensions of the thyristor.
There is a large degree of freedom in designing the transistor, and since it is connected between the gate and cathode of a P-channel MOS transistor, there is no need to reduce the width of W''-1, and it is easy to handle large currents. It is easy to manufacture because it only requires a relatively large planar dimension that is approximately the same as that of an SI thyristor.

FIG. 11 shows yet another embodiment of the present invention, which is an example of a double gate SI sirinuta having a first gate or cut gate structure and a second gate or surface gate structure. P+ as in Figure 8
Region 31 is the first gate φ − gate region, n+ region is the second gate region, n+ region 23 is the cathode region, P+ region 32 is the auxiliary cathode region, P+
Region 21 is the anode region, and n+ region 43 is the auxiliary anode region. In FIG. 8, a P-channel MOS has a gate electrode 25 on one side of the convex portion where the cathode is formed.
In FIG. 11, P-channel MOS transistors are formed on both sides of the convex portion.
The on-resistance is smaller than that in the case shown in FIG. P
Since the + region 31 is formed on the entire surface of the bottom of the cut, it is easier to manufacture than in the case of FIG. 8 where it is formed on the side wall of the cut. A potential barrier against electrons injected from the cathode is formed near the central portion of the first gate region 31, and by applying a positive potential to the first gate electrode 25, the potential of this potential barrier can be reduced to the gate level. capacitive coupling through the membrane 26, and at the same time the second
A negative potential is applied to the gate electrode 51, and the double gate SI thyristor is turned on to form a potential barrier against holes from the anode. The turn-off is performed by a P-channel MOS transistor formed between the cathode and the first gate, and an N-channel transistor formed between the 7-node and second gate.
This is done by setting the gate potential of the channel transistor transistor to zero to turn on each MOS transistor, extracting holes from the first gate and electrons from the second gate, and increasing the potential of each potential barrier. . Figure 11.

Inside the n+ cathode region 23 there is a p+ auxiliary cup)' region [
Of course, it is also possible to use a structure similar to that shown in FIG. 7, which includes 32 parts. As explained in FIG. 8, it goes without saying that the structure of the first gate side of this embodiment can be applied to a notched gate type single gate SI thyristor in which the structure of the second gate side is omitted; In this case, the anode side may have an anode short structure shown in FIG. 6 or an n-buffer structure shown in FIG. 7.

Furthermore, as described in the explanation of FIG. 8, various modifications such as making the first gate a normal junction gate structure and making the second gate a notched gate type insulation control are also possible within the scope of the present invention. I'll come.

Although FIGS. 8 and 11 show cut grooves in the vertical sidewalls, V-shaped or inverted mesa-type cut grooves may be used.

12 and 13 show an embodiment in which the present invention is applied to a buried gate S ethyristor, and FIG. 12(b) and FIG. 13(b) show FIG. 12(a) and FIG. Fig. 5a shows a cross section along beta' of a). The cross-sectional views of FIGS. 12(b) and 13(b) show the P+ gate region 31.
is divided into a multi-channel structure,
When viewed in plan view, the P+ gate region 31 is continuous and integrated.

Turn-on lowers the potential barrier to electrons at the center of each channel by applying a positive potential to the gate electrode 25 of the MOS diode, which is composed of the oxide film 26 at the bottom of the groove, the P+ gate region 31, and the gate electrode 25. It is done by The capacitance of the MOS diode at the bottom of the groove is determined by the P+ gate region 31 of the SI thyristor.
In the case of a buried gate structure, since the junction capacitance of the gate is relatively large, it is desirable that the thickness of the oxide film at the bottom of the trench be less than Lz1ooi. Turn-off is performed from the p+ gate region by setting the potential of the gate electrode 25 of the depletion type P-channel MOS transistor whose drain is the p+ auxiliary cathode region 32 adjacent to the n+ cathode region 23 and whose source is the P+ gate region 31 to zero. It is done by pulling out the hole. Fig. 12(b) and Fig. 13 fb) show an S■ anode short structure in which the p+ anode region 21 is divided and the n+ region 41 is inserted between them, but if the turn-off time can be delayed, A uniform anode structure in which the n+ region 41 is omitted may be used, or if Tilmi flow during turn-off is a problem, a double gate structure may be used. Compared to FIG. 12, the one shown in FIG. 13 has more margin around the cathode region and is easier to manufacture.

〔Effect of the invention〕

According to the present invention, there is no need to use positive and negative power supplies for trigger pulses and quench pulses, and the gate can be driven using a simple square wave, which simplifies the drive circuit and also facilitates the design of the drive circuit. Therefore, the number of parts in the drive circuit can be reduced, making it inexpensive and easy to maintain. Further, according to the present invention, fast switching can be performed with a gate current that is sufficiently small compared to the anode current, and since the gate is cut off in terms of direct current, gate loss is extremely small. According to the present invention, it can be manufactured very easily since it can be manufactured by making a small modification to the conventional SI SI risk process, such as adding the step of forming an auxiliary cathode region or an auxiliary anode region.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram showing a conventional SI thyristor driving method, Fig. 2 is an equivalent circuit in which 2MO8 is connected between the gate and cathode, Fig. 3 is an example of a conventional insulated gate SI thyristor, and Figs. Figure 13 is an embodiment of the present invention, Figure 6 is S
I anode tuple gate SI thyristor, Fig. 8fb)
are equivalent to 23... cathode region, 21... anode region. 31...First gate region, 42...Second gate region, 26...Insulating film, 5...First gate electrode, 1...Second gate electrode for exporters ``Tairizizitoboshakyu'' came (α) (b) Jizu (α) () Gezuzuzuzu (a) (b) Sudazu, Rozuzu evil, 72rlA 73 Kaku

Claims (6)

[Claims] (1) First conductivity type high impurity density first semiconductor region (2
1; 23), a second semiconductor region (22) with a low impurity density formed adjacent to the first semiconductor region, and a second semiconductor region (22) formed on a part of the surface of the second semiconductor region. a conductive type high impurity density third semiconductor region (23; 21); an interior of the third semiconductor region or adjacent to the third semiconductor region; and a part of the surface of the second semiconductor region; A fourth semiconductor region (32; 4) of the first conductivity type formed in
3) and a fifth semiconductor region (31; 42) of a first conductivity type with a high impurity density formed on a part of the surface of the second semiconductor region and separated from the fourth semiconductor region. , an insulating film (26 ) and an insulated gate control electrode (25; 51) formed on the upper part of the insulating film, the first semiconductor region is the first main electrode region and the second semiconductor region is the first main electrode region. A static induction thyristor with a second main electrode region. (2) The fifth semiconductor region is formed in a part of the sidewall of a recess formed on the surface of the second semiconductor region, and at least a common part of the insulated gate control electrode is formed inside the recess. The electrostatic induction thyristor according to claim 1, characterized in that: (3) The electrostatic induction thyristor according to claim 1, wherein the fifth semiconductor region is formed so as to sandwich or surround the third semiconductor region with at least a few common parts. (4) the first main electrode region or the anode region;
4. The electrostatic induction thyristor according to claim 1, wherein the main electrode region is a cathode region. (5) The first main electrode region is a cathode region, and the second main electrode region is a cathode region.
The electrostatic induction thyristor according to any one of claims 1 to 3, wherein the main electrode region is an anode region. (6) a first conductivity type low impurity density semiconductor substrate (22); a first conductivity type cathode region (23) formed on a part of the first main surface of the semiconductor substrate; an auxiliary cathode region (32) of a second conductivity type formed inside or adjacent to the cathode region; and a first main surface of the semiconductor substrate in the vicinity of the cathode region and spaced apart from the auxiliary cathode region. a first gate region (31) of a second conductivity type formed in a part of the auxiliary cathode region (31) on the upper surface of the first gate region and the first main surface of the semiconductor substrate; A first layer is formed on the portion sandwiched between the gate regions with an insulating film (26) interposed therebetween.
a gate electrode (25), an anode region (21) of a second conductivity type formed in a part of a second main surface of the semiconductor substrate opposite to the first main surface, and an anode region (21) formed in the inside or outside of the anode region a first electrode formed adjacent to the anode region;
a conductive type auxiliary anode region (43); a first conductive type auxiliary anode region (43) formed near the anode region, spaced apart from the said auxiliary anode region, and formed on a part of the second main surface of the semiconductor substrate; 2 gate region (42), an insulating film on the upper part of the surface of the second gate region and the part of the second main surface of the semiconductor substrate sandwiched between the auxiliary anode region and the second gate region. An electrostatic induction thyristor characterized in that it is a double-gate thyristor co-constructed with a second gate electrode (51) formed through a second gate electrode (26).