JPH03296325A - Adaptive equalizer - Google Patents

Abstract

PURPOSE:To disperse signals by connecting a matching filter composed of a multi-branching signal and a discrimination feedback equalizer in cascade to form an adaptive equalizer and synthesizing multi-branching signals optimizingly in response to the fluctuation of a propagation line. CONSTITUTION:A received signal is branched into 3-branch signals via delay circuit 7, 8. The signal passing through the delay circuit 7 is used as a reference signal and given to an adder circuit 9. Signals being one preceding and one succeeding time slot signals with respect to the reference signal and a zero signal (signalX0) whose amplitude is 0 are inputted to a selective circuit 10, tap coefficients C-1, C1 of a transversal filter of a next stage are monitored by using the control signal of a control circuit 11 to discriminate whether a wave is an advanced interference wave or a delayed interference wave, the selective circuit 10 selects one preceding and one succeeding time slot signals added to a reference signal and outputs an optimum signal, which is inputted to the adder 9. The control circuit 11 receives a reception signal before being inputted to a matching filter and a signal after being discriminated, generates a selective signal by the detection of correlation and outputs the control signal to the selective circuit 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an adaptive equalizer, and particularly to adaptive equalization using a matched filter and a transversal filter used for equalizing signals via a communication line. Concerning vessels.

[Conventional technology]

In the field of digital communication, especially in communication systems that use wireless communication transmission channels, the received signal is a composite of signals propagated through different routes caused by multiple reflected waves, which are interference waves, in addition to the direct wave. To equalize this signal, a Tonpersal type equalizer that performs equalization on the time axis is suitable.

The transversal equalizer includes a plurality of cascade-connected delay elements, a plurality of weighting circuits to which respective inputs or outputs of the plurality of delay elements are connected, and the plurality of weighting circuits. An adder circuit that combines the signals at the output end, and a control that generates a control signal (weighting is a coefficient) that is applied to the multiple weighting circuits so that the added output from the adder circuit is equalized to a desired value. This is an equalizer equipped with a circuit that equalizes the distortion of the received signal due to multiple reflected waves.

FIG. 4 is a block diagram of a conventional baseband digital processing decision feedback type equalizer, which is an application of a transversal equalizer. A received signal digitized by an A/D converter is input. The buses 11 are designated path 2, path 3, and path 4 in order from the MSB (most significant bit) side of the A/D converter output. The transversal filter consists of a delay circuit 16, 17, 18, 19 which delays the received signal by l time slots, and a weighting circuit 20, 21, 22, 23, 24 connected to each tap. The control signal for the weighting circuit is controlled by a control circuit 28. The path outputs of the C-2 tap, C-1 tap, CO tap, C2 tap, and CI tap are input to an adder 25.

This addition output (feedforward output) is input to the next adder 27, and at the same time the output of the adder 27 becomes the equalizer output, the delay circuit 18.19 and the weighting circuit connected to the equalizer output is input to a feedback filter (not shown) constituted by circuits 23 and 24 and an adder 26 that adds the equalizer a.

FIG. 5 shows a configuration diagram of an example of the control circuit 28. As shown in FIG.

In FIG. 4, the filter 30 is a signal of path 1 shown by a solid line in FIG. The signal of path 3 shown by the dashed line in FIG. 6, which represents the polarity of the intersymbol interference (error) and the intersymbol interference (error), is input.

In other words, assuming that the four-valued sign is a signal with two values on the positive voltage side and two values on the negative voltage side with Ov as the reference, the signal of path l divides the received voltage range into thirds, so it is either positive voltage or negative voltage. You will need to identify the voltage. Since path 2 is further divided into thirds, the quaternary code can be identified by path] and path 2. pass 3
further divides the range divided by path 2 into thirds, so it shows how far the received voltage deviates from the signal identification level. In the figure, the identification results are obtained in order from the most significant bit of path 1.

In the control circuit 28 of FIG. 4, l time slot delay circuits are prepared for the number of taps in the signal path of path I or path 3, and the products of path 1 and path 3 are calculated in different cycle periods. This multiplication output is integrated over a required time slot to generate a control signal.

That is, the identification signal obtained from the input of the filter 30 is input to the cascade-connected l time slot delay circuits 3 and 32, and the error signal obtained from the output of the filter 30 is input to the l time slot delay circuits 33 and 34. Multiplier 35 multiplies the identification signal and error signal extracted from them.
．． 36.37.38.39 and its output is integrated circuit 4
It integrates by 0.41.42.43.44 and outputs tap coefficients (C-2, C-1, Co, CI, C2), respectively.

In the case of the above configuration, the output of the adder 26 in FIG. 4 is C-2
Intersymbol interference related to taps, C-1 taps, and CO taps is reduced.

[Problem to be solved by the invention]

In conventional equalizers, if the reflected wave arrives ahead of the direct wave with a large amplitude in time, the intersymbol interference used for the C-1 tap will be the largest, but it will not be judged for the C-1 tap input signal. There was a problem that the equalization ability could not be improved because the signal could not be input.

The present invention has been made in view of the above points, and is an adaptive system that takes advantage of the characteristics of the decision feedback equalizer and is configured entirely with digital circuits even when an interference wave with a larger amplitude ratio than the main signal arrives in advance. The purpose is to provide an equalizer.

[Means to solve the problem]

In an adaptive equalizer used for equalizing signals in wireless communication, from the input terminal and output terminal of each of a plurality of delay circuits each having a delay time of l time slots and to which a baseband or intermediate frequency input signal is supplied. Among the extracted multi-branch signals, one branch signal extracted from a delay circuit in the middle of the plurality of delay circuits is inputted as a reference signal to an adder circuit, and each signal in the time slot before and after the reference signal is selected. Alternatively, a matched filter configured to input the weighted signal to the adder circuit and take out the output signal from the adder circuit can be used to provide a baseband signal with equalization characteristics to reduce intersymbol interference. Provided on the input side.

[Effect]

By constructing an adaptive equalizer by cascading a matched filter and a decision feedback equalizer each having a multi-branch signal input, signal dispersion is achieved by optimally combining multi-branch signals according to propagation path fluctuations.

During steady state, the reference signal is output as is, and when the interference wave arrives late, the reference signal and the branch output signal from one time slot before are combined and output.

Furthermore, if the interference wave has advanced and arrives, the reference signal and the branch output signal after one time slot are combined and output. In particular, when the interference wave has the same amplitude as the direct wave, the magnitude of the interference wave can be dispersed in half, and the intersymbol interference after dispersion is equalized by cascade-connected decision feedback equalizers.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.
) is a first embodiment in which a matched filter and a decision feedback equalizer 5 are configured in the baseband. In the figure, 1 is a received signal, 2 is a receiver, 3 is a demodulator, 4 is a matched filter, and 5 is a container. After the received RF signal l is amplified and frequency-converted by a receiver 2, it is synchronously detected by a demodulator 3, and signal equalized by a matched filter 4 and a decision feedback equalizer 5.

The decision feedback equalizer 5 has the same configuration as that of the conventional baseband digital processing decision feedback type vase shown in FIG. 5 described above. Reference numeral 100 in FIG. 1 denotes the adaptive equalizer of the first embodiment, which is configured to use a matched filter 4 and a decision feedback type equalizer 5 in combination.

FIG. 1(B) is a block diagram of a second embodiment of the present invention in which a matched filter 6 is provided in the intermediate frequency stage, and only the decision feedback equalizer 5 has a baseband configuration. Received signal 1 is sent to receiver 2
After being amplified and frequency converted by , signal processing is performed by a matched filter 6 in an intermediate frequency band, and synchronous detection is performed by a demodulator 3 .

The demodulated signal is subjected to signal equalization by a decision feedback equalizer 5 at the next stage. The decision feedback equalizer 5 has the same configuration as the conventional baseband digital processing decision feedback equalizer shown in FIG. 4 described above. Reference numeral 200 in FIG. 1 is an adaptive equalizer of the second embodiment, which is configured to use a matched filter 6, a demodulator 3, and a decision feedback equalizer 5 in combination.

FIG. 2 shows a matched filter 4 which forms the main part of the embodiment of the present invention.
6 shows the configuration of the first embodiment. The received signal passes through a delay circuit 7.8 to generate three branches of signals. The signal that has passed through the delay circuit 7 is used as a reference signal and is input to the adder circuit 9. A signal before and after one time slot of the reference signal and a zero signal whose amplitude value is 0 (signal XO) are input to the selection circuit IO, and the tap coefficients C-1, The CI is monitored to determine whether it is a leading interference wave or a delayed interference wave, and a selection circuit 10 selects signals before and after the time slot to be added to the reference signal, outputs an optimal signal, and inputs it to an adder 9. The addition output of the reference signal and selection signal is input to the decision feedback equalizer 5 in FIG. 1 at the next stage. The control circuit 11 receives the received signal before being input to the matched filter and the signal after the determination, generates a selection signal through correlation detection, and outputs the control signal to the selection circuit IO.

FIG. 3 shows a block diagram of a second embodiment of the matched filter. The received signal passes through a delay circuit 7.8 to generate a multi-branch signal. The reference signal that has passed through the delay circuit 7 is input to the adder 14 as is. The main signal is input to the control circuit, and the weighting signals D1 and D are output from the control circuit.
The weighting is inputted to the circuit 12 and the weighting is inputted to the circuit 13, respectively, and the signals before and after one time slot of the reference signal are converted into the optimal signal by the weighting circuit 12 and 13, and the weighting is converted to the optimal signal by the adder. 14 and synthesized with the above reference signal. This composite signal is input to the decision feedback equalizer 5 in FIG. 1 at the next stage. The control circuit 11 receives the received signal before inputting the matched filter and the signal after the judgment, generates a selection signal by detecting the correlation, and outputs the addition of the reference signal and the selection signal to the next stage, the judgment feedback equalizer 5 shown in FIG. Enter.

In the above embodiment, the delay circuit 7.8 has a delay amount T corresponding to the clock cycle of the data signal, that is, one time slot.
The present invention is also applicable to a matched filter composed of a delay circuit of T/n (n natural number).

〔Effect of the invention〕

As described above, according to the present invention, even when a reflected wave with a large amplitude ratio arrives in advance, the interference component due to the branch output signal after one time slot is dispersed, especially when the interference wave has the same amplitude as the direct wave. Since the interference wave can be dispersed into 172 waves, the residual intersymbol interference can be equalized by the decision feedback equalizer in the next stage, which is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram of a first embodiment of a matched filter, Fig. 3 is a block diagram of a second embodiment of a matched filter, and Fig. 4 is a block diagram of a conventional matched filter. A configuration diagram of a baseband digital processing decision feedback equalizer, Figure 5 is a configuration diagram of an example of a control circuit, and Figure 6 is a diagram showing signal discrimination levels when a received signal is divided into four levels. be. 4.6... Matched filter, 5... Decision feedback equalizer,
7.8...Delay circuit, 9...Addition circuit, 10...
Selection circuit, 11... Control circuit, 12.13... Weighting circuit, 30... Filter, 31.32.33.3
4...Delay circuit, 40.41.42.43.44...
・Integrator circuit.

Claims (1)

[Claims] In an adaptive equalizer used for equalizing wireless communication signals, each of a plurality of delay circuits each having a delay time of one time slot and to which a baseband or intermediate frequency input signal is supplied. Among the multi-branch signals taken out from the input end and the output end, one branch signal taken out from a delay circuit in the middle of the plurality of delay circuits is input to the addition circuit as a reference signal, and the time before and after the reference signal is A matched filter configured to select or weight each signal of the slot and input it to the adder circuit and take out the output signal from the adder circuit is given equalization characteristics to reduce intersymbol interference to the baseband signal. An adaptive equalizer characterized in that it is provided on the input side of a decision feedback equalizer.