JPH0330151U

JPH0330151U -

Info

Publication number: JPH0330151U
Application number: JP8879889U
Authority: JP
Priority date: 1989-07-28
Filing date: 1989-07-28
Publication date: 1991-03-25

Description

[Brief explanation of drawings]

図面は本考案の一実施例を示すもので、第１図
は回路構成を示すブロツク図、第２図は第１図に
おける表データ記憶部の記憶構成を示す図、第３
図はキー入力操作例と表示内容との対応関係を示
す図、第４図は表の作成例を示す図、第５図ａ〜
ｄは表データ入力に集計処理及びソート処理を示
す図、第６図は入力処理を示すフローチヤート、
第７図は演算処理１の詳細を示すフローチヤート
、第８図は合計ページ作成処理の詳細を示すフロ
ーチヤート、第９図は集計処理の詳細を示すフロ
ーチヤート、第１０図は演算処理２の詳細を示す
フローチヤート、第１１図は合計ページ検索処理
の詳細を示すフローチヤート、第１２図は登録処
理の詳細を示すフローチヤート、第１３図は編集
の処理動作を示すフローチヤート、第１４図は並
べ替え終了後の表を示す図である。１１……制御部、１２……キー入力部、１３…
…入力バツフア、１４……入力・編集データ記憶
部、１５……表データ記憶部、１６……アドレス
制御部、１６ａ……挿入アドレス記憶部、１６ｂ
……上限アドレス記憶部、１７……属性データ判
断部、１８……演算・比較部、１９……表示デー
タ記憶部、２０……表示部、２１……演算データ
記憶部、２１ａ……未演算フラグカウンタ、２１
ｂ……合計ページカウンタ、２１ｃ……合計コー
ドカウンタ、２２……アドレスレジスタ、２３ａ
……挿入アドレス記憶部、２３ｂ……上限アドレ
ス記憶部、２３ｃ……集計先頭アドレス記憶部、
２３ｄ……演算ページアドレス記憶部、２３ｅ…
…登録処理アドレス記憶部、３１……表インデツ
クス記憶エリア、３２……項目データ記憶エリア
、３３……表データ記憶エリア。 The drawings show one embodiment of the present invention; FIG. 1 is a block diagram showing the circuit configuration, FIG. 2 is a diagram showing the storage configuration of the table data storage section in FIG. 1, and FIG.
The figure shows the correspondence between key input operation examples and display contents, Figure 4 shows an example of creating a table, and Figures 5 a -
d is a diagram showing aggregation processing and sorting processing in tabular data input, FIG. 6 is a flowchart showing input processing,
Figure 7 is a flowchart showing details of calculation process 1, Figure 8 is a flowchart showing details of total page creation process, Figure 9 is a flowchart showing details of aggregation process, and Figure 10 is a flowchart showing details of calculation process 2. Flowchart showing the details, FIG. 11 is a flowchart showing details of total page search processing, FIG. 12 is a flowchart showing details of registration processing, FIG. 13 is a flowchart showing editing processing operation, FIG. 14 FIG. 2 is a diagram showing a table after sorting is completed. 11...Control unit, 12...Key input unit, 13...
...Input buffer, 14...Input/edit data storage section, 15...Table data storage section, 16...Address control section, 16a...Insertion address storage section, 16b
... Upper limit address storage section, 17 ... Attribute data judgment section, 18 ... Calculation/comparison section, 19 ... Display data storage section, 20 ... Display section, 21 ... Calculation data storage section, 21a ... Not calculated flag counter, 21
b...Total page counter, 21c...Total code counter, 22...Address register, 23a
...Insertion address storage section, 23b...Upper limit address storage section, 23c...Tally start address storage section,
23d...Calculation page address storage unit, 23e...
...Registration processing address storage unit, 31...Table index storage area, 32...Item data storage area, 33...Table data storage area.

Claims

[Scope of Claim for Utility Model Registration] An item setting means for setting a plurality of items in an arbitrary arrangement; an attribute setting means for setting an attribute for each item set by this means; means for inputting data for each set item; and processing means for processing the data input for each of the above items in priority order according to the arrangement order of the items according to the attributes set for each item. A table data processing device comprising: means for arbitrarily changing the arrangement order of the setting items; and means for causing the processing means to perform processing when the arrangement is changed by the means.