JPH0330306B2 - - Google Patents
Info
- Publication number
- JPH0330306B2 JPH0330306B2 JP59278879A JP27887984A JPH0330306B2 JP H0330306 B2 JPH0330306 B2 JP H0330306B2 JP 59278879 A JP59278879 A JP 59278879A JP 27887984 A JP27887984 A JP 27887984A JP H0330306 B2 JPH0330306 B2 JP H0330306B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- semiconductor region
- insulated gate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔技術分野〕
本発明はサージ電圧に対して絶縁ゲートの破壊
強度を向上せしめた絶縁ゲート型集積回路装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an insulated gate integrated circuit device in which the breakdown strength of an insulated gate against surge voltage is improved.
従来のトランジスタ、或いはトランジスタおよ
び抵抗素子などの複数の回路素子を集積化した半
導体集積回路などのPN接合を有する半導体装置
は、これに印加される予期せぬサージ電圧によつ
てしばしば破壊される場合がある。この予期せぬ
サージ電圧は例えば半導体装置の運搬時の人体か
らの静電気の誘導、或いはそれらの半導体装置を
テレビセツトなどの電子機器に応用した場合にそ
の応用回路機器の周辺回路からの好ましくないサ
ージ電圧の誘導に起因し、好ましくないこのサー
ジ電圧は、半導体装置に設けられた信号の入出力
端子、或いは接地端子などの外部接続用端子か
ら、半導体装置のPN接合部に印加され、該PN
接合を破壊するものである。
Semiconductor devices with PN junctions, such as conventional transistors or semiconductor integrated circuits that integrate multiple circuit elements such as transistors and resistive elements, are often destroyed by unexpected surge voltages applied to them. There is. This unexpected surge voltage can be caused, for example, by the induction of static electricity from the human body during transportation of semiconductor devices, or by undesirable surges from the peripheral circuits of the applied circuit equipment when these semiconductor devices are applied to electronic equipment such as television sets. This undesirable surge voltage due to voltage induction is applied to the PN junction of the semiconductor device from a signal input/output terminal provided on the semiconductor device or an external connection terminal such as a ground terminal, and the PN
It destroys the bond.
特に、MOS型素子すなわち絶縁ゲート型半導
体素子を有する集積回路装置においては、外部入
力端子からのサージ電圧によりそこに接続される
半導体素子の絶縁ゲートが破壊されやすいことか
ら、抵抗素子を含むゲート保護回路装置を形成せ
しめるが、サージ電圧によつてそのゲート保護回
路装置の抵抗素子自体が破壊し、ゲート保護の機
能を全く達成できないという問題がある。 In particular, in integrated circuit devices that have MOS type elements, that is, insulated gate type semiconductor elements, the insulated gates of the semiconductor elements connected to them are easily destroyed by surge voltage from external input terminals, so gate protection including resistive elements is required. Although a circuit device is formed, there is a problem in that the resistance element itself of the gate protection circuit device is destroyed by the surge voltage, and the gate protection function cannot be achieved at all.
本発明の目的は、半導体素子本来の特性を損傷
することなく、サージ電圧に対し破壊強度の強い
絶縁ゲート型集積回路装置を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide an insulated gate integrated circuit device that has high breakdown strength against surge voltages without damaging the inherent characteristics of semiconductor elements.
本発明のさらに他の目的は、半導体素子を形成
するための半導体チツプ内の占有面積を極力小さ
くせしめたサージ電圧に対する破壊強度の強い絶
縁ゲート型集積回路装置を提供することにある。 Still another object of the present invention is to provide an insulated gate integrated circuit device which minimizes the area occupied within a semiconductor chip for forming semiconductor elements and has high breakdown strength against surge voltages.
本発明の絶縁ゲート型集積回路装置によれば、
次の構成より成る。 According to the insulated gate integrated circuit device of the present invention,
It consists of the following composition.
(イ) 一主面をもつ第１導電型の第１の半導体領域
内の一部に形成された第２導電型のソースおよ
びドレイン半導体領域、ならびにそれらソース
およびドレイン半導体領域間の前記第１の半導
体領域を覆つて絶縁ゲート膜を介して配設され
たゲート電極を有する絶縁ゲート型半導体素
子；
(ロ) 前記第１の半導体領域内の他の部分におい
て、所定の不純物濃度をもつて延在するように
形成された第２導電型のゲート保護用抵抗領
域；
(ハ) 前記抵抗領域の一端部に接続され、該一端部
を外部入力端子に電気的に接続するための第１
の接続導体および前記抵抗領域の他端部に接続
され、該他端部を前記ゲート電極に電気的接続
するための第２接続導体；
(ニ) 前記抵抗領域の一端部を包囲し、かつ、前記
第１の半導体領域に対してPN接合を形成する
前記抵抗領域より低不純物濃度の第２導電型の
耐圧補強領域；および
(ホ) 前記抵抗領域の一端部より前記他端部に近い
部分の前記第１の半導体領域と前記抵抗領域の
他端部との間に電気的接続され、かつ、前記絶
縁ゲート膜の破壊電圧より低いPN接合耐圧を
有するPN接合部。(a) A source and drain semiconductor region of a second conductivity type formed in a part of a first semiconductor region of a first conductivity type having one main surface, and the first semiconductor region between the source and drain semiconductor regions. an insulated gate type semiconductor element having a gate electrode disposed through an insulated gate film covering a semiconductor region; (b) extending with a predetermined impurity concentration in another part of the first semiconductor region; a second conductivity type gate protection resistor region formed to
and a second connection conductor connected to the other end of the resistance region and electrically connecting the other end to the gate electrode; (d) surrounding one end of the resistance region, and a breakdown voltage reinforcing region of a second conductivity type having a lower impurity concentration than the resistance region and forming a PN junction with the first semiconductor region; and (e) a portion closer to the other end than to one end of the resistance region; A PN junction electrically connected between the first semiconductor region and the other end of the resistance region, and having a PN junction breakdown voltage lower than a breakdown voltage of the insulated gate film.
本発明の一実施例を図面を参照にして説明す
る。第１図および第２図は、本発明のMOS型集
積回路装置、すなわち、絶縁ゲート型集積回路装
置で、第２図その断面図、第１図は、その等価回
路図をそれぞれ示す。第１図中、３１は、Ｎ型半
導体基板である。３７は、Ｐ型ソース領域で導体
２０１を通して接地される、３８はＰ型ドレイン
領域でVDDに接続される。３４は、外部入力端子
３２と、ゲート２０２間に接続されるＰ型のゲー
ト保護用抵抗領域である。３３は、抵抗領域３４
より濃度の低いP-型の低濃度領域で、外部入力
端子３２のコンタクト部３５直下に形成されてい
る。この構成にすれば外部入力端子３２に予期せ
ぬサージ電圧が印加されても、ゲート保護用抵抗
領域３４には、低濃度のP-型領域３３があるた
め、この抵抗領域３４とＮ型半導体基板３１との
間のPN接合で消費されるエネルギーが減少され
るため、このゲート保護用抵抗領域３４の破壊強
度は向上する。さらに、コンタクト部３５直下
に、P-型領域があるために、P-型領域によつて
包囲された以外のゲート保護用抵抗領域３４が基
板３１に対し形成するPN接合は絶縁ゲート２０
３の破壊電圧より低い所望のツエナー電圧に設定
できるので、ゲート２０２に印加されるサーをツ
エナー電圧に制限する。すなわち、ゲート保護用
抵抗領域３４のサージ電圧をクランプするという
本発明の特性を損うことなく、抵抗領域３４自体
のサージ電圧に対する破壊強度を改善することが
できる。しかも、P-領域３３は局部的に設けら
るので、集積度を著しく悪化されることはない。
An embodiment of the present invention will be described with reference to the drawings. 1 and 2 show a MOS type integrated circuit device, that is, an insulated gate type integrated circuit device according to the present invention, FIG. 2 is a sectional view thereof, and FIG. 1 is an equivalent circuit diagram thereof, respectively. In FIG. 1, 31 is an N-type semiconductor substrate. 37 is a P-type source region which is grounded through the conductor 201, and 38 is a P-type drain region which is connected to V DD . 34 is a P-type gate protection resistance region connected between the external input terminal 32 and the gate 202. 33 is a resistance region 34
This is a P - type low concentration region with a lower concentration, and is formed directly below the contact portion 35 of the external input terminal 32 . With this configuration, even if an unexpected surge voltage is applied to the external input terminal 32, since the gate protection resistor region 34 has a low concentration P - type region 33, this resistor region 34 and the N-type semiconductor Since the energy consumed in the PN junction with the substrate 31 is reduced, the breakdown strength of the gate protection resistive region 34 is improved. Further, since there is a P - type region directly below the contact portion 35, the PN junction formed with the substrate 31 by the gate protection resistance region 34 other than that surrounded by the P - type region is connected to the insulated gate 20.
Since the desired Zener voltage can be set lower than the breakdown voltage of No. 3, the voltage applied to the gate 202 is limited to the Zener voltage. That is, the breakdown strength of the resistance region 34 itself against surge voltage can be improved without impairing the characteristic of the present invention of clamping the surge voltage of the gate protection resistance region 34. Furthermore, since the P - region 33 is provided locally, the degree of integration will not be significantly degraded.
以上の説明から明らかなように、本発明によれ
ば、ゲート保護用抵抗領域の外部入力端子側には
高耐圧化されたPN接合部を電気的接続し、その
ゲート電極側には絶縁ゲートの破壊耐圧よりも低
いクランプ電圧を有するPN接合部を電気的接続
した形態をとることを特徴としている。このた
め、抵抗領域の濃度は、ゲート保護回路の回路定
数またはソースおよびドレイン領域のような他の
半導体領域の濃度に合せて設定することが可能と
なり、集積回路の設計に自由度を与えることがで
きる。 As is clear from the above description, according to the present invention, a high voltage PN junction is electrically connected to the external input terminal side of the gate protection resistance region, and an insulated gate is connected to the gate electrode side. It is characterized by having a form in which a PN junction having a clamping voltage lower than the breakdown voltage is electrically connected. Therefore, the concentration of the resistance region can be set according to the circuit constant of the gate protection circuit or the concentration of other semiconductor regions such as the source and drain regions, giving flexibility in the design of integrated circuits. can.
第１図および第２図は、本発明の絶縁ゲート型
集積回路装置（MOS型集積回路）を示し、第２
図はその断面図、第１図はその等価回路図であ
る。
３１……Ｎ型半導体基板（Ｎ型半導体領域）、
３７……ソース半導体領域、３９……ドレイン半
導体領域、３２……外部入力端子、３３……耐圧
補強領域、３４……抵抗領域、３５……コンタク
ト部、３６……出力信号線、３７……ソース領
域、３８……ドレイン領域、２０１……ソース接
地線、２０２……ゲート電極、２０３……絶縁ゲ
ート膜。
1 and 2 show an insulated gate integrated circuit device (MOS integrated circuit) of the present invention, and FIG.
The figure is a sectional view thereof, and FIG. 1 is an equivalent circuit diagram thereof. 31...N-type semiconductor substrate (N-type semiconductor region),
37... Source semiconductor region, 39... Drain semiconductor region, 32... External input terminal, 33... Voltage reinforcement region, 34... Resistance region, 35... Contact portion, 36... Output signal line, 37... Source region, 38...Drain region, 201...Source ground line, 202...Gate electrode, 203...Insulated gate film.
Claims (1)
置： (イ) 一主面をもつ第１導電型の第１の半導体領域
内の一部に形成された第２導電型のソースおよ
びドレイン半導体領域、ならびにそれらソース
およびドレイン半導体領域間の前記第１の半導
体領域を覆つて絶縁ゲート膜を介して配設され
たゲート電極を有する絶縁ゲート型半導体素
子； (ロ) 前記第１の半導体領域内の他の部分におい
て、所定の不純物濃度をもつて延在するように
形成された第２導電型のゲート保護用抵抗領
域； (ハ) 前記抵抗領域の一端部に接続され、該一端部
を外部入力端子に電気的接続するための第１の
接続導体および前記抵抗領域の他端部に接続さ
れ、該他端部を前記ゲート電極に電気的接続す
るための第２の接続導体； (ニ) 前記抵抗領域の一端部を包囲し、かつ、前記
第１の半導体領域に対してPN接合を形成する
前記抵抗領域より低不純物濃度の第２導電型の
耐圧補強領域；および (ホ) 前記抵抗領域の一端部より前記他端部に近い
部分の前記第１の半導体領域と前記抵抗領域の
他端部との間に電気的接続され、かつ、前記絶
縁ゲート膜の破壊電圧より低いPN接合耐圧を
有するPN接合部。[Claims] 1. An insulated gate integrated circuit device having the following configuration: (a) A second conductive type integrated circuit device formed in a part of a first conductive type first semiconductor region having one main surface. (b) an insulated gate semiconductor element having a source and drain semiconductor region and a gate electrode disposed via an insulated gate film to cover the first semiconductor region between the source and drain semiconductor regions; (b) the first semiconductor region; a second conductivity type gate protection resistor region formed to extend with a predetermined impurity concentration in another portion of the semiconductor region; (c) connected to one end of the resistor region; A first connecting conductor for electrically connecting one end to an external input terminal; and a second connecting conductor connected to the other end of the resistance region and electrically connecting the other end to the gate electrode. (d) a breakdown voltage reinforcing region of a second conductivity type that surrounds one end of the resistance region and has a lower impurity concentration than the resistance region and forms a PN junction with the first semiconductor region; ) electrically connected between the first semiconductor region in a portion closer to the other end than the one end of the resistance region and the other end of the resistance region, and lower in breakdown voltage than the insulated gate film; PN junction with PN junction withstand voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59278879A JPS60246662A (en) | 1984-12-28 | 1984-12-28 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59278879A JPS60246662A (en) | 1984-12-28 | 1984-12-28 | semiconductor equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50117710A Division JPS5916413B2 (en) | 1975-10-01 | 1975-10-01 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60246662A JPS60246662A (en) | 1985-12-06 |
| JPH0330306B2 true JPH0330306B2 (en) | 1991-04-26 |
Family
ID=17603384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59278879A Granted JPS60246662A (en) | 1984-12-28 | 1984-12-28 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60246662A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CH599085A5 (en) * | 1974-03-01 | 1978-05-12 | Hoffmann La Roche |
-
1984
- 1984-12-28 JP JP59278879A patent/JPS60246662A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60246662A (en) | 1985-12-06 |
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