JPH0330328B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a digital data signal transmission device, 0
When a large number of consecutive value bits occur, some of them are replaced with past data and bits that have a fixed conversion rule before being transmitted, thereby facilitating bit synchronization in transmission and reception and duplication of the original signal.

[Industrial application field]

The present invention is an improvement of a continuous zero suppression method for transmission data.

When the receiving side receives data sent through a transmission path, it cannot be received correctly unless the correct position of each bit of the binary signal, which is the smallest unit of data, is known. Therefore, the exact time position of each bit is obtained by the bit period.

If the input data changes randomly, synchronization can be achieved by extracting a bit timing signal from the zero crossing point, for example. However, if the data contains consecutive zero-value bits, there is a risk that a timing signal may not be obtained, so it is necessary to suppress consecutive zeros in the data.

[Conventional technology]

Conventionally, the scrample method and the zero suppression method have been used.
The nB1C method is being considered.

In the former, by randomizing the transmission data sequence and sending it out, the receiving side performs signal processing that does not bias the frequency toward a specific frequency, and extracts timing for bit synchronization.

In the latter case, an additional bit is provided after each code, and by giving this bit a polarity opposite to that of the last bit of the code, the occurrence of consecutive zeros on the receiving side is prevented.

[Problem that the invention seeks to solve]

Since the above scrambling method achieves randomization in changes in a long data sequence and averaging of signal change points, it is not possible to completely suppress continuous zeros.

Additionally, the nB1C method requires additional bits.
Since the number of bits of each code increases, the bit rate increases, which has the disadvantage of reducing transmission efficiency.

[Means for solving problems]

The above problem requires a means for detecting a pattern of N consecutive bits at 0, and a means for detecting a pattern of N consecutive bits at 0, and a means for detecting a pattern of N consecutive bits at 0, and a means for detecting a pattern of N consecutive bits including the bit immediately before the start of the 0. This problem is solved by the zero consecutive suppression method of the present invention, which comprises means for replacing the data with k bits containing at least one 1 in reverse order.

[Effect]

According to the present invention, when N 0-value bits exceeding the allowable limit of zero consecutive patterns are detected,
At least one of the bits is changed to 1 and sent out. Therefore, the transmission efficiency does not deteriorate and zero suppression is perfect. On the receiving side, since a data signal with an amplitude change point is always obtained within the permissible time, it is easy to extract the bit synchronization signal.

Furthermore, among the N 0-value bits, the k bits replaced on the transmitting side are the past data arranged in reverse order, so when receiving, the corresponding bits in the received data can be compared. Therefore, it is possible to know whether or not bit conversion has been performed on the transmitting side, and it is easy to convert the converted bits back to the original 0 and reproduce the original data.

〔Example〕

The present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 shows an example of a data pattern configuration in which bit conversion is performed according to the present invention to suppress consecutive zeros, FIG. FIG. 2 is a waveform time chart for explaining the operation of the transmitting section, FIG. 4 is an example of the configuration of the receiving section of the continuous zero suppression device, and FIG. 5 is a waveform time chart for explaining the operation of the receiving section of FIG. be.

In this embodiment, N=16 is selected, and when 16 consecutive 0s occur, one bit is always converted to the value 1 and transmitted.

In FIG. 1, the original signal data pattern on the transmitting side is shown in the first row. The original signal has the value 1 at the n+3rd bit, and then 16 consecutive bits become 0.

The original signal data pattern needs to be converted, and the first row shows the data pattern after the conversion process on the transmitting side. In the case shown, the trailing 2 of 16 consecutive 0 bits
A forced conversion process is being performed on the bit.

The conversion is related to past data, and in this example, the 15th bit of consecutive zeros corresponds to the n+3rd bit of the past data, and the 16th bit of consecutive zeros corresponds to the n+2nd bit of the past data. It is converted as follows. That is, the 15th bit of consecutive 0's is given the value 1, and the 16th bit is given the value a.

The received data on the receiving side has a general data pattern as shown in the first row. That is, the received data pattern has 14 consecutive 0 bits followed by converted 2 bits Y1 and Y2.

Incidentally, even if there is no bit conversion, the same configuration may occur if, for example, the original data pattern has 14 consecutive zeros.

However, the original data can be accurately reproduced by comparing the Y1 and Y2 bits with past data according to the transmission side conversion rule and returning the Y1 and Y2 bits to 0 only when they match.

Note that if a data pattern that does not have bit conversion is received as if it were a pattern that has undergone regular conversion, there is a risk that it will be erroneously inversely converted. It can be easily solved using technology.

The operation of the continuous zero suppression system will be explained according to the configuration diagram of the transmitting section shown in FIG.

The transmitting section is composed of a hexadecimal counter 2, a delay flip-flop (hereinafter referred to as D-FF), 3, 4, 5-7, switch circuits 8, 9, etc.

When the input transmission data signal is level '1', 1
The hexadecimal counter 2 is reset by being given a load signal of '0' level from the NOR gate 1.

When the input transmit data signal is level '0', 16
Advance counter 2 counts clock pulses and counts 16 clock pulses.
When the count is completed, the 17th input transmit data signal
Outputs ripple carry RC at bit time.
A part of this output is passed through the NOR gate 1 as a load signal LD to return the counter to its initial state, and the other part is given to the switches 8 and 9 as a switch control signal via the D-FFs 3 and 4. When the switch control signal goes to level '1', the switch is moved to a lower position different from that shown.

5, 6, and 7 are D-FFs that delay input data by 3 bits, 15 bits, or 2 bits, respectively.

The ripple carry output of the hexadecimal counter is D-
It is delayed by 1 bit by FF3 and applied to switch 8, and further delayed by 1 bit by D-FF4 and applied to switch 9.

If the input data signal of 0 continues for 16 bits, the input data signal becomes 0.
The start bit of is counted as the 1st bit, and switch 8
causes a transition at the 18th bit, delayed by the 17th bit. Since the input signal is delayed by 18 bits by the D-FFs 5 and 6, the input data signal one bit before the first bit of the original data signal is connected to the output section. This data signal corresponds to the '1' level signal that last reset the hexadecimal counter.

Switch 9 switches at the 19th bit with a delay of 18 bits, and the data signal bit delayed by 20 bits in D-FFs 5 to 7, that is, the first bit of the original data signal.
The data signal 2 bits before the bit is output. This data signal corresponds to the data signal one bit before the '1' level signal that last reset the hexadecimal counter.

In the operational waveform diagram of FIG. 3, the 1st row shows the input transmission data signal waveform.

In the case shown in the figure, the data indicates level '1' and then becomes 0 for 16 consecutive bits.

The first row is a ripple carry RC, which is a signal that is output when the hexadecimal counter counts 16. It is branched at the output of counter 2, and part of it passes through gate 1 and becomes the load signal for the hexadecimal counter in the first row. Reset.

A similar load signal is
Also given when 1'.

The first row shows the switching signal S1 which is applied to the switch 8 by delaying the output signal of the counter 2 by 1 bit by D-FF3.

The first row is the switching signal S2 of the switch.

The first row shows the data signal x sent out from the transmit data output with a delay of 3 bits. This signal is a 3-bit delayed version of the input transmission data signal in the row.

The th row is a signal y which is delayed by 18 bits from the input transmission data signal in the th column.

The th row is a signal z obtained by delaying the transmission data input signal of the th column by 20 bits.

The output signal of the column is constructed as follows. The signal x in the row is output until the y signal is output as transmission data by the switching signal S1, and when the transmission data input is the 17th bit, the y signal in the row is sent to the transmission data output section by switch 8. sent,
This inserts level '1'. Connection is 1
Only during the bit period.

Further, when the transmission data input reaches the 18th bit, the switch S2 sends the z signal of the row to the transmission data output section. The z signal is inserted into the transmission data only for one bit period.

Of the 16 consecutive 0 bits in the transmission data signal in the 1st row, the latter 2 bits are replaced with a converted signal that has a certain relationship with the original data signal, and the 14th bit '0'
A '1' level bit is inserted next to the level bit to prevent consecutive '0' levels.

FIG. 4 is a block diagram of the receiving section.

In the figure, 21 and 33 are NOR gates, 22 is
Hexadecimal counter, 24 and 34 are AND gates, 23,
25 to 28, 31, and 32 are D-FFs, and 29 and 30 are exclusive NOR gates. Exclusive NOR gate 29 has two inputs, one of which receives a signal delayed by 16 bits of the input received data signal, and the other input receives a signal delayed by 1 bit.

The two input sections of the exclusive NOR gate 30 include a terminal for inputting the input received data signal as it is without any delay, and a terminal for inputting a signal delayed by 17 bits.

The outputs of gates 29 and 30 are fed to AND gate 24.

Ripple carry RC of hexadecimal counter 22 is 1
The signal is bit delayed and supplied to AND gate 24, turning gate 24 on. At this time, if the first bit is the bit at which 0 level continuity starts in the original input received data signal, it becomes the 16th bit.

The AND gate 24 is a circuit that logically combines the original data signal with the bits converted and added when there are N consecutive zero bits from the received data signal on the transmitting side, and generates a signal for inverse conversion. This is a signal regeneration circuit. The operation of these circuits is illustrated in FIG.

The first line is the input received data signal, with 0 on the sending side.
The received signal is shown when 16 consecutive signals are received. The 15th bit of the received signal is converted to a ``1'' level, and the 16th bit is converted to be equal to the level of the data bit two bits before the first bit.

The first row shows the ripple carry output of the counter 2. This output is divided into two parts, and one part is supplied as a reset signal to the load terminal of the counter 22 via the gate 21 as a signal shown in the first row, and the other part is sent to the D-FF 23. The signal is supplied to the AND gate 24 as the waveform of the signal row delayed by one bit.

As inputs to the exclusive NOR gate 29, the 1-bit delayed input received data signal in the first row and the 16-bit delayed input received data signal shown in the second row are supplied.

As inputs to the exclusive NOR gate 30, the input received data signal without bit delay in the row 1 and the input received data signal delayed by 17 bits shown in the row 1 are supplied.

The '1' level signal in the row from D-FF23 is
When applied to AND gate 24, gate 29
Then, on the transmitting side, a ``1'' level signal is generated by logical calculation between the ``1'' level signal inserted into the zero sequence and the ``1'' level signal before the 0 sequence, and this is given to the gate 24. In addition, the gate 30 generates a ``1'' level signal by logical calculation of the bit signal one bit before the ``1'' level signal of the original data signal and the 16th bit signal obtained by converting and adding this, and this is sent to the gate. Give to 24.

Thus, at the 16th bit of the input received data signal, the ``1'' level signal of the row is produced as the output of the AND gate 24.

The signal from the gate 24 is delayed by one bit by the D-FFs 31 and 32 and then supplied to the NOR gate 33.

A 2-bit wide '0' level signal for the second row is generated from the NOR gate 33 and is supplied to the AND gate 34. The AND gate 34 receives a column signal and a row signal, which are obtained by delaying the input received data signal by 2 bits. The signal from the NOR gate 33 acts to block the AND gate 34 at the position of the additional signal of the 15th and 16th bits of the data signal of the row, converting the 15th and 16th bits to ``0'' level.

The signal in the first row represents the output signal of gate 34.

〔Effect of the invention〕

The present invention completely suppresses continuous 0 bits without increasing the transmission bit rate and facilitates generation of a synchronization signal on the receiving side, and its effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data pattern for continuous zero suppression according to the present invention, FIG. 4 is a block diagram showing an embodiment of the receiving section of the zero consecutive suppression device according to the present invention, and FIG. 5 is a waveform time chart for explaining the operation of the receiving section in FIG. 4. This is a waveform time chart. In the figure, 1 is a NOR gate, 2 is a hexadecimal counter, 3, 4, 5-7 are D-FF circuits, 8, 9 are switch circuits, 21, 23 are NOR gates, 22
is a hexadecimal counter, 23, 25 to 28, 31 and 32 are D-FF circuits, 24 and 34 are AND gates,
29 and 30 are exclusive NOR gates.

Claims (1)

[Claims] The rear k consecutive bits of a pattern consisting of N consecutive 10 bits are past data of consecutive k bits including the bit immediately before the start of the 0. A continuous zero suppression method characterized in that k bits including at least one 1 are replaced in reverse order.