JPH033034U - - Google Patents
Info
- Publication number
- JPH033034U JPH033034U JP7827288U JP7827288U JPH033034U JP H033034 U JPH033034 U JP H033034U JP 7827288 U JP7827288 U JP 7827288U JP 7827288 U JP7827288 U JP 7827288U JP H033034 U JPH033034 U JP H033034U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- voltage
- level
- interrupt
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013256 coordination polymer Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Power Sources (AREA)
Description
第１図は、本考案の停電瞬断処理装置を示すブ
ロツク図、第２図は、本装置の動作に用いる電圧
変動グラフ、第３図は、同装置の動作フローチヤ
ート、第４図は、電圧変動を示すグラフである。
２ａ……第１の比較手段、２ｂ……第２の比較
手段、３ａ……第１の基準電圧設定器、３ｂ……
第２の基準電圧設定器、４……判定手段、４ａ…
…タイマ手段、４ｂ…比較手段、５……リセツト
手段。
Fig. 1 is a block diagram showing the instantaneous power outage processing device of the present invention, Fig. 2 is a voltage fluctuation graph used for the operation of this device, Fig. 3 is an operation flowchart of the device, and Fig. 4 is: It is a graph showing voltage fluctuation. 2a...first comparison means, 2b...second comparison means, 3a...first reference voltage setter, 3b...
Second reference voltage setter, 4...determination means, 4a...
...Timer means, 4b...Comparison means, 5...Reset means.
Claims (1)
Ｕに割込み処理を発生させ、リセツトレベル部分
でＣＰＵをリセツトする停電瞬断処理装置におい
て： ＣＰＵの割込みレベルを検出する第１の比較手
段２ａと； ＣＰＵのリセツトレベルを検出する第２の比較
手段２ｂと； 第１の比較手段の出力により所定時間掲示する
とともに、この時間のタイムアツプを検出する判
定手段４と； 第２の比較手段あるいは、判定手段の出力によ
りＣＰＵをリセツトするリセツト手段５と；を具
備し、電圧が割込みレベル以下であつても所定時
間以内にリセツトレベルまで降下しない場合、Ｃ
ＰＵの演算処理を続行させることを特徴とする停
電瞬断処理装置。[Scope of claim for utility model registration] Voltage changes to CP at interrupt level due to voltage fluctuation.
In an instantaneous power outage processing device that generates an interrupt process in U and resets the CPU at the reset level part: a first comparison means 2a that detects the CPU interrupt level; and a second comparison means that detects the CPU reset level. 2b; Judgment means 4 for displaying for a predetermined period of time based on the output of the first comparing means and detecting time-up of this time; Resetting means 5 for resetting the CPU based on the output of the second comparing means or the judging means; If the voltage does not drop to the reset level within a predetermined time even if the voltage is below the interrupt level, the C
A power outage instantaneous interruption processing device characterized by continuing arithmetic processing of a PU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7827288U JPH033034U (en) | 1988-06-15 | 1988-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7827288U JPH033034U (en) | 1988-06-15 | 1988-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033034U true JPH033034U (en) | 1991-01-14 |
Family
ID=31621396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7827288U Pending JPH033034U (en) | 1988-06-15 | 1988-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033034U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63103311A (en) * | 1986-10-20 | 1988-05-09 | Victor Co Of Japan Ltd | Processing method for microcomputer system at time of service interruption |
-
1988
- 1988-06-15 JP JP7827288U patent/JPH033034U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63103311A (en) * | 1986-10-20 | 1988-05-09 | Victor Co Of Japan Ltd | Processing method for microcomputer system at time of service interruption |
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