JPH0330996B2 - - Google Patents
Info
- Publication number
- JPH0330996B2 JPH0330996B2 JP60109366A JP10936685A JPH0330996B2 JP H0330996 B2 JPH0330996 B2 JP H0330996B2 JP 60109366 A JP60109366 A JP 60109366A JP 10936685 A JP10936685 A JP 10936685A JP H0330996 B2 JPH0330996 B2 JP H0330996B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- gallium arsenide
- emitter
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/36—Unipolar devices
- H10D48/362—Unipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunnelling transistors [RTT], bulk barrier transistors [BBT], planar doped barrier transistors [PDBT] or charge injection transistors [CHINT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
- H10D62/605—Planar doped, e.g. atomic-plane doped or delta-doped
Landscapes
- Bipolar Transistors (AREA)
Description
〔産業上の利用分野〕
本発明は半導体装置、特に新しく開発されつつ
ある、THETA（Tunneling Hot Electron
Transfer Amplifier）或いはHET（Hot
Electron Transistor）と呼ばれる半導体装置の
改善に関する。
現在マイクロエレクトロニクスは目覚ましい進
歩を続けいるが、更にこれを飛躍させるめに、従
来のトランジスタとは異なる動作原理に基づく新
しい半導体装置を実現する研究が行われている。
前記HETはこの様な新しい動作原理に基づく
半導体装置であるが、そのベースコンタクトには
後述の如き問題点がありその解決が強く要望され
ている。
〔従来の技術〕
先に提案されたHETでは、第２図ａのポテン
シヤル図に示す動作が行われる。（M.Heiblum；
1980IEEE Electron Devices Meeting）
すなわち本装置はエミツタ、ベース、コレクタ
の３領域を備え、ベースとエミツタ及びコレクタ
との間にそれぞれポテンシヤルバリアが設けられ
ている。この装置に例えば温度77Kにおいて、エ
ミツタをベースに対して負の電位とするバイアス
電圧を加えたとき、電子がエミツタ−ベース間の
バリアをトンネル効果により突き抜けて、エミツ
タ電流IEを構成する。
この電子は相互にほぼ等しいエネルギーをも
ち、ベース領域においてはエミツタ−ベース間の
電位差VBEによつて伝導帯端に対してeVBEだけ高
いエルギー準位にある。このエネルギーをもつ電
子はコレクタに向かつて弾動的に進むが、電子相
互間、電子−格子原子間及び電子−不純物原子間
の衝突を総合したこの方向（Ｘ方向）の平均自由
行程をleとするとき、長さdBのベース領域を電子
が通過する確率はexp（−dB／le）である。
ベース領域に対する前記コレクタ側のバリア高
さをφc、電子ビームのエネルギーの正常な幅の1/
２をδとして、電子の前記エネルギー準位差のＸ
成分がφc＋δより大であるときは、エミツタ電流
IEの大部分はコレクタ側のバリアφcをを越え、ベ
ース接地電流増幅率α＝Ic／IEを１に漸近させる
ことが出来る。
このHETを半導体装置として実現した従来例
の模式側断面図を第２図ｂに示す。
同図おいて、２１は半絶縁性砒化ガリウム
（GaAs）基板、２２，２８及び２９はn+型GaAs
コンタクト層、２３はｎ型GaAsコレクタ層、２
４は砒化アルミニウムガリウム（AlGaAs）バリ
ア層、２５はｎ型GaAsベース層、２６は
AIGaAsバリア層、２７はｎ型GaAsエミツタ層、
３０はコレクタ電極、３１はベース電極、３２は
エミツタ電極、３３は保護絶縁膜である。
本従来例の半導体基板のコレクタ層２３乃至エ
ミツタ層２７は例えば下記例の如く構成されてい
る。
[Industrial Field of Application] The present invention relates to semiconductor devices, particularly to the newly developed THETA (Tunneling Hot Electron
Transfer Amplifier) or HET (Hot
Concerning improvements to semiconductor devices called electron transistors. Currently, microelectronics continues to make remarkable progress, and in order to make further advances, research is being conducted to realize new semiconductor devices based on operating principles different from those of conventional transistors. Although the HET is a semiconductor device based on such a new operating principle, its base contact has problems as described below, and a solution to these problems is strongly desired. [Prior Art] In the previously proposed HET, the operation shown in the potential diagram of FIG. 2a is performed. (M. Heiblum;
1980 IEEE Electron Devices Meeting) That is, this device has three areas: an emitter, a base, and a collector, and potential barriers are provided between the base, emitter, and collector, respectively. When a bias voltage is applied to this device to make the emitter a negative potential with respect to the base at a temperature of, for example, 77 K, electrons penetrate the barrier between the emitter and the base due to the tunnel effect, forming an emitter current I E. These electrons have approximately the same energy, and in the base region, due to the emitter-base potential difference V BE , they are at an energy level higher than the conduction band edge by eV BE . Electrons with this energy move elastically toward the collector, but the mean free path in this direction (X direction), which combines collisions between electrons, between electrons and lattice atoms, and between electrons and impurity atoms, is l e Then, the probability that an electron passes through the base region of length d B is exp(-d B / le ). The barrier height on the collector side with respect to the base region is φ c , 1/of the normal width of the energy of the electron beam.
2 as δ, X of the energy level difference of the electrons
When the component is larger than φ c + δ, the emitter current
Most of I E exceeds the barrier φ c on the collector side, and the common base current amplification factor α=I c /I E can be made to asymptotically approach 1. A schematic side sectional view of a conventional example in which this HET is realized as a semiconductor device is shown in FIG. 2b. In the figure, 21 is a semi-insulating gallium arsenide (GaAs) substrate, 22, 28 and 29 are n + type GaAs
contact layer, 23 is n-type GaAs collector layer, 2
4 is aluminum gallium arsenide (AlGaAs) barrier layer, 25 is n-type GaAs base layer, 26 is
AIGaAs barrier layer, 27 is n-type GaAs emitter layer,
30 is a collector electrode, 31 is a base electrode, 32 is an emitter electrode, and 33 is a protective insulating film. The collector layer 23 to emitter layer 27 of the semiconductor substrate of this conventional example are constructed as shown in the example below, for example.
以上説明した如く、HETのベース電極を分す
るために表出させるベース層に生ずる表面空乏
層、或いはバリア層からベース層に達する空乏
層、及び一旦表出したベース層のコンタクト再生
長層との界面近傍に生ずる低電子濃度のデイプリ
ーシヨン領域によつて、そのベース抵抗が増大し
ている。
この新しい半導体装置に期待される特性を実現
するために、ベース抵抗増大の要因を排除し、か
つ煩雑なベースコンタクト層の選択的再成長のプ
ロセスを必要としない構造の改善が要望されい
る。
〔問題点を解決するための手段〕
前記問題点は、半絶縁性砒化ガリウム基板上
に、ｎ型砒化ガリウム・コレクタコンタクト層、
ｎ型砒化ガリウム・コレクタ層、ノンドープの砒
化アルミニウムガリウム第１バリア層、ベース
層、ノンドープの砒化アルミニウムガリウム第２
バリア層、ｎ型砒化ガリウム・エミツタ層、ｎ型
砒化ガリウム・エミツタコンタクト層が順次積層
され、該ベース層はｎ型砒化ガリウム層と、シリ
コンのアトミツクプレーンドーピング層と、ノン
ドープの砒化ガリウム層とが順次積層されてな
り、かつ該コレクタコンタクト層、該ベース層及
び該エミツタコンタクト層に接して金ゲルマニウ
ム／金よりなるコレクタ電極、ベース電極及びエ
ミツタ電極がそれぞれ設けられて、該エミツタ電
極を該ベース電極に対し負の電位とし、該ベース
電極を該コレクタ電極に対し負の電位とするバイ
アス電圧を加えて、電子を該エミツタ層から該第
２バリア層をトンネル効果により突き抜け、ホツ
トエレクトロ状態で該ベース層を通過し該第１バ
リア層のポテンシヤルレベルを越えて、該コレク
タ層に到達させる本発明による半導体装置により
解決される。
〔作用〕
本発明によれば、ベース層の上側すなわちベー
ス電極側の界面近傍に、シリコンSiをアトミツク
プレーンドーピング（atomic plane doping）し
て非常に高濃度のキヤリア電子を生する。
なおベース層には従来と同様にドナー不純物を
均等にドーピングするが、アトミツクプレーンド
ーピングによるキヤリア電子が分布する領域に
は、この通常のドーピングは行つても、行わなく
てもよい。
このアトミツクプレーンドーピングによる高濃
度のキヤリア電子により空乏層の伸長は止めら
れ、かつベース電極を直接ベース層上に形成して
も良好なオーミツク接触が得られて、ベース抵抗
の低減が実現される。
〔実施例〕
以下本発明を実施例により具体的に説明する。
第１図ａは本発明の実施例の模式側断面図、同図
ｂはその要部拡大図である。
同図において、１は半絶縁性GaAs基板、２乃
至８は下記のエピタキシヤル成長層、１０はコレ
クタ電極、１１はベース電極、１２はエミツタ電
極、１３は保護絶縁膜である。
本実施例において各エピタキシヤル成長層２乃
至８は、半絶縁性GaAs基板１上に例えば下記例
の如く分子線エピタキシヤル成長方法により順次
エピタキシヤル成長されている。
なおベース層５の成長は次の３段階で行われて
いる。すなわち、As，Ga，Siビームによりｎ型
GaAs層５ａを厚さ48mmに成長した後にGaビーム
を止め、Siを面濃度約３×1012cm-2にアトミツク
プレーンドーピングし５ｂ、次いでSiビームを止
めGaビームを再び入射させてノンドープのGaAs
層５ｃを厚さ２mmに長し、合計厚さを50nmとし
ている。
As explained above, the surface depletion layer that occurs in the base layer exposed to separate the base electrode of the HET, or the depletion layer that reaches the base layer from the barrier layer, and the contact regrowth layer of the base layer once exposed. The base resistance increases due to the depletion region of low electron concentration that occurs near the interface. In order to achieve the characteristics expected of this new semiconductor device, there is a need for an improved structure that eliminates the factors that increase base resistance and eliminates the need for a complicated selective regrowth process of the base contact layer. [Means for solving the problem] The above problem is solved by forming an n-type gallium arsenide collector contact layer on a semi-insulating gallium arsenide substrate,
n-type gallium arsenide collector layer, undoped aluminum gallium arsenide first barrier layer, base layer, undoped aluminum gallium arsenide second
A barrier layer, an n-type gallium arsenide emitter layer, and an n-type gallium arsenide emitter contact layer are sequentially laminated, and the base layer includes an n-type gallium arsenide layer, an atomic plane doping layer of silicon, and an undoped gallium arsenide layer. are sequentially laminated, and a collector electrode, a base electrode, and an emitter electrode made of gold germanium/gold are provided in contact with the collector contact layer, the base layer, and the emitter contact layer, respectively, and the emitter electrode is By applying a bias voltage that makes the base electrode a negative potential and the base electrode a negative potential with respect to the collector electrode, electrons pass through the second barrier layer from the emitter layer by a tunnel effect, forming a hot electro state. This problem is solved by the semiconductor device according to the present invention, in which the voltage passes through the base layer, exceeds the potential level of the first barrier layer, and reaches the collector layer. [Operation] According to the present invention, a very high concentration of carrier electrons is generated by atomic plane doping of silicon on the upper side of the base layer, that is, near the interface on the base electrode side. The base layer is uniformly doped with donor impurities as in the prior art, but this normal doping may or may not be performed in the region where carrier electrons are distributed due to atomic plane doping. The expansion of the depletion layer is stopped by the high concentration of carrier electrons resulting from this atomic plane doping, and even if the base electrode is formed directly on the base layer, a good ohmic contact can be obtained and the base resistance can be reduced. . [Example] The present invention will be specifically described below with reference to Examples.
FIG. 1a is a schematic side sectional view of an embodiment of the present invention, and FIG. 1b is an enlarged view of the main part thereof. In the figure, 1 is a semi-insulating GaAs substrate, 2 to 8 are epitaxial growth layers described below, 10 is a collector electrode, 11 is a base electrode, 12 is an emitter electrode, and 13 is a protective insulating film. In this embodiment, the epitaxial growth layers 2 to 8 are epitaxially grown one after another on a semi-insulating GaAs substrate 1 by, for example, a molecular beam epitaxial growth method as shown in the example below. Note that the growth of the base layer 5 is performed in the following three stages. In other words, the As, Ga, and Si beams
After growing the GaAs layer 5a to a thickness of 48 mm, the Ga beam is stopped, Si is atomically plane doped to a surface concentration of about 3×10 12 cm -2 5b, and then the Si beam is stopped and the Ga beam is made incident again to form a non-doped layer. GaAs
The layer 5c is 2 mm thick and has a total thickness of 50 nm.
以上説明した如く本発明によれば、ベース抵抗
が低減されて電流増幅率等の特性が改善され、か
つ選択的成長が不要となり、これによつてHET
の開発が大きく前進する効果が得られる。
As explained above, according to the present invention, the base resistance is reduced, characteristics such as current amplification factor are improved, and selective growth is not required, thereby making it possible to improve HET
This will have the effect of greatly advancing the development of
第１図ａは本発明の実施例を示す模式側断面
図、ｂはその要部拡大図、第２図ａは本装置の動
作の説明図、ｂは従来例を示す模式側断面図であ
る。
図において、１は半絶縁性GaAs基板、２及び
８はn+型GaAsコンタクト層、３はｎ型GaAsコ
レクタ層、４はAlGaAsバリア層、５は５ａ乃至
５ｃよりなるベース層、５ａはｎ型GaAs層、５
ｂはSiアトミツクプレーンドープ層、５ｃはノン
ドープのGaAs層、６はAlGaAsバリア層、７は
ｎ型GaAsエミツタ層、１０はコレクタ電極、１
１はベース電極、１２はエミツタ電極、１３は保
護絶縁膜を示す。
Fig. 1a is a schematic side sectional view showing an embodiment of the present invention, b is an enlarged view of the main part thereof, Fig. 2a is an explanatory diagram of the operation of the present device, and b is a schematic side sectional view showing a conventional example. . In the figure, 1 is a semi-insulating GaAs substrate, 2 and 8 are n + type GaAs contact layers, 3 is an n-type GaAs collector layer, 4 is an AlGaAs barrier layer, 5 is a base layer consisting of 5a to 5c, and 5a is an n-type GaAs layer, 5
b is a Si atomic plane doped layer, 5c is a non-doped GaAs layer, 6 is an AlGaAs barrier layer, 7 is an n-type GaAs emitter layer, 10 is a collector electrode, 1
1 is a base electrode, 12 is an emitter electrode, and 13 is a protective insulating film.
Claims (1)
ガリウム・コレクタコンタクト層２、ｎ型砒化ガ
リウム・コンタクト層３、ノンドープの砒化アル
ミニウムガリウム第１バリア層４、ベース層５、
ノンドープの砒化アルミニウムガリウム第２バリ
ア層６、ｎ型砒化ガリウム・エミツタ層７、ｎ型
砒化ガリウム・エミツタコンタクト層８が順次積
層され、該ベース層５はｎ型砒化ガリウム層５ａ
と、シリコンのアトミツクプレーンドーピング層
５ｂと、ノンドープの砒化ガリウム層５ｃとが順
次積層されてなり、かつ該コレクタコンタクト層
２、該ベース層５及び該エミツタコンタクト層８
に接して金ゲルマニウム／金よりなるコレクタ電
極１０、ベース電極１１及びエミツタ電極１２が
それぞれ設けられて、該エミツタ電極１２を該ベ
ース電極１１に対し負の電位とし、該ベース電極
１１を該コレクタ電極１０に対し負の電位とする
バイアス電圧を加えて、電子を該エミツタ層７か
ら該第２バリア層６をトンネル効果により突き抜
け、ホツトエレクトロン状態で該ベース層５を通
過し該第１バリア層４のポテンシヤルレベルを越
えて、該コレクタ層３に到達させることを特徴と
する半導体装置。1 On a semi-insulating gallium arsenide substrate 1, an n-type gallium arsenide collector contact layer 2, an n-type gallium arsenide contact layer 3, a non-doped aluminum gallium arsenide first barrier layer 4, a base layer 5,
A non-doped aluminum gallium arsenide second barrier layer 6, an n-type gallium arsenide emitter layer 7, and an n-type gallium arsenide emitter contact layer 8 are sequentially laminated, and the base layer 5 is formed by an n-type gallium arsenide layer 5a.
, an atomic plane doped layer 5b of silicon, and a non-doped gallium arsenide layer 5c are sequentially laminated, and the collector contact layer 2, the base layer 5, and the emitter contact layer 8
A collector electrode 10, a base electrode 11, and an emitter electrode 12 made of gold germanium/gold are respectively provided in contact with the emitter electrode 12, and the emitter electrode 12 is set at a negative potential with respect to the base electrode 11, and the base electrode 11 is connected to the collector electrode. 10, electrons pass through the second barrier layer 6 from the emitter layer 7 due to the tunneling effect, pass through the base layer 5 in the form of hot electrons, and pass through the first barrier layer 4. A semiconductor device characterized in that the potential level of the semiconductor device is exceeded to reach the collector layer 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60109366A JPS61268063A (en) | 1985-05-23 | 1985-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60109366A JPS61268063A (en) | 1985-05-23 | 1985-05-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61268063A JPS61268063A (en) | 1986-11-27 |
| JPH0330996B2 true JPH0330996B2 (en) | 1991-05-01 |
Family
ID=14508412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60109366A Granted JPS61268063A (en) | 1985-05-23 | 1985-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61268063A (en) |
-
1985
- 1985-05-23 JP JP60109366A patent/JPS61268063A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61268063A (en) | 1986-11-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |