JPH0331076Y2 - - Google Patents
Info
- Publication number
- JPH0331076Y2 JPH0331076Y2 JP10597181U JP10597181U JPH0331076Y2 JP H0331076 Y2 JPH0331076 Y2 JP H0331076Y2 JP 10597181 U JP10597181 U JP 10597181U JP 10597181 U JP10597181 U JP 10597181U JP H0331076 Y2 JPH0331076 Y2 JP H0331076Y2
- Authority
- JP
- Japan
- Prior art keywords
- tantalum
- thin film
- gold
- integrated circuit
- lower layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
本考案は薄膜集積回路装置に係り、特に薄膜基
板上にペレツトをマウントする場合において、ペ
レツトの接着強度を向上する技術に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film integrated circuit device, and particularly to a technique for improving the adhesive strength of pellets when mounting the pellets on a thin film substrate.
従来、薄膜基板の導体部にペレツトを接着する
のに、Agペースト等の導電性樹脂を接着剤とし
て使用する方法がある。一般に、薄膜基板上に形
成されたマウントランドの上層には、導電性によ
り金が使用されている。しかし、金は周知の通り
不活性であるため、接着剤との接着強度が弱いと
いう難点がある。したがつて、従来、基板に急激
な、又は過度の熱などが加わつたりすると、熱応
力等により接着強度が劣化する傾向にある。 Conventionally, there is a method of using a conductive resin such as Ag paste as an adhesive to bond pellets to the conductor portion of a thin film substrate. Generally, gold is used for the upper layer of a mount land formed on a thin film substrate due to its conductivity. However, since gold is inert as is well known, it has the disadvantage of weak adhesive strength with adhesives. Therefore, conventionally, when sudden or excessive heat is applied to the substrate, the adhesive strength tends to deteriorate due to thermal stress or the like.
本考案の目的は、このような従来の欠点を除去
した。接着強度が劣化しない薄膜集積回路装置を
提供することにある。 The purpose of the present invention is to eliminate such conventional drawbacks. An object of the present invention is to provide a thin film integrated circuit device whose adhesive strength does not deteriorate.
本考案の特徴は、セラミツク基板上に導電性樹
脂でペレツトを接着するマウントランドを有する
薄膜集積回路装置において、前記マウントランド
はタンタルの下層と金の上層とを有し、該タンタ
ルの下層は該マウントランドの全面に形成され、
その上の金の上層は格子状に形成されこれにより
該格子間に該タンタルの下層が複数の角状で露出
して接着面となつている薄膜集積回路装置にあ
る。 The present invention is characterized by a thin film integrated circuit device having a mounting land for bonding pellets with conductive resin on a ceramic substrate, wherein the mounting land has a lower layer of tantalum and an upper layer of gold, and the lower layer of tantalum has a lower layer of tantalum. Formed on the entire surface of Mount Land,
The upper layer of gold thereon is formed in a lattice pattern such that the lower layer of tantalum is exposed in a plurality of corners between the lattices and provides a bonding surface in a thin film integrated circuit device.
以下、本考案の一実施例について、図面と共に
説明する。第１図は本考案実施例の薄膜集積回路
装置の部分平面図、第２図は第１図のＡ−A′で
の断面図である。まず、セラミツク基板３上に、
タンタル膜２、導体膜１として金を順次、スパツ
タ法により形成し、その後、図のように導体膜だ
けをエツチングにより除去する。従つてタンタル
膜が接着剤の付着面となる。タンタルは金と比べ
て接着剤との接着強度が強いため、従来の全面金
膜で形成されたマウントランドと比較してペレツ
トの接着強度が向上する。また、熱による影響に
対しても、熱線膨張係数が金よりも小さくペレツ
トの熱線膨張係数に近いため熱応力が減少され、
接着強度の劣化の傾向も小さくなる。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partial plan view of a thin film integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line A-A' in FIG. First, on the ceramic substrate 3,
Gold is sequentially formed as a tantalum film 2 and a conductor film 1 by sputtering, and then only the conductor film is removed by etching as shown in the figure. Therefore, the tantalum film becomes the adhesive surface. Since tantalum has a stronger adhesive strength than gold, the adhesive strength of the pellet is improved compared to the conventional mount land formed entirely of gold film. In addition, with respect to the effects of heat, thermal stress is reduced because the coefficient of linear thermal expansion is smaller than that of gold and close to that of pellets.
The tendency for adhesive strength to deteriorate is also reduced.
本考案は以上説明した作用により、薄膜基板の
導体部とペレツトとの導電性を害うことなく、ペ
レツトの接着強度を向上させるものである。 The present invention improves the adhesion strength of the pellets without impairing the conductivity between the conductive portion of the thin film substrate and the pellets through the effects described above.
第１図は本考案の薄膜集積回路装置の一実施例
の部分平面図、第２図は第１図のＡ−A′での断
面図である。
なお図において、１……導体膜、２……タンタ
ル膜、３……セラミツク基板、である。
FIG. 1 is a partial plan view of an embodiment of the thin film integrated circuit device of the present invention, and FIG. 2 is a sectional view taken along line A-A' in FIG. In the figure, 1... conductor film, 2... tantalum film, 3... ceramic substrate.
Claims (1)
着するマウントランドを有する薄膜集積回路装置
において、前記マウントランドはタンタルの下層
と金の上層とを有し、該タンタルの下層は該マウ
ントランドの全面に形成され、その上の金の上層
は格子状に形成されこれにより該格子間に該タン
タルの下層が複数の角状で露出して接着面となつ
ていることを特徴とする薄膜集積回路装置。 In a thin film integrated circuit device having a mount land on which a conductive resin is bonded to a pellet on a ceramic substrate, the mount land has a lower layer of tantalum and an upper layer of gold, and the lower layer of tantalum is formed on the entire surface of the mount land. A thin film integrated circuit device characterized in that the upper gold layer thereon is formed in the form of a lattice, so that the lower layer of tantalum is exposed in a plurality of corner shapes between the lattices and serves as an adhesive surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10597181U JPS5812942U (en) | 1981-07-16 | 1981-07-16 | Thin film integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10597181U JPS5812942U (en) | 1981-07-16 | 1981-07-16 | Thin film integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5812942U JPS5812942U (en) | 1983-01-27 |
| JPH0331076Y2 true JPH0331076Y2 (en) | 1991-07-01 |
Family
ID=29900488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10597181U Granted JPS5812942U (en) | 1981-07-16 | 1981-07-16 | Thin film integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5812942U (en) |
-
1981
- 1981-07-16 JP JP10597181U patent/JPS5812942U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5812942U (en) | 1983-01-27 |
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