JPH0332243A - Monitor equipment - Google Patents

Abstract

PURPOSE:To attain matching processing with lots of collation patterns without defect of the collation processing as to one signal frame by installing the hardware for exclusive collation processing so as to execute the collation processing by the hardware. CONSTITUTION:The equipment is provided with a flag detection circuit 2 detecting a flag pattern of a reception signal from a line relay reception circuit 1, a byte composing circuit 4, and a pattern collation circuit 3 exclusive for frame pattern collation processing. When a change from the flag pattern to a discharge flag pattern is detected by the flag detection circuit 2, the pattern collation circuit 3 reads the reception signal byte and the head byte of the collation pattern and the mask pattern to apply the collation in the unit of bytes. A pattern collation memory 31 stores plural collation an mask patterns for each address block, reads the head byte of each address block with respect to one reception signal byte and collates them. Thus, the matching processing with lots of collation patterns is applied as to one signal frame without missing of the collation processing.

Description

[Detailed Description of the Invention] [Summary] Regarding the monitoring of a line that sends and receives information using a flag-synchronized transmission method, hardware dedicated to matching processing is provided, and a large number of matching patterns can be generated without missing matching processing for one signal frame. In order to monitor the signal frames of the flag-synchronized serial transmission method, the line relay receiving circuit is equipped with a flag detection circuit that detects the flag pattern of the received signal, and a byte that assembles the signal frame one byte at a time. It comprises an assembly circuit and a pattern matching circuit dedicated to frame pattern matching processing, and the pattern matching circuit includes a pattern matching memory that stores matching patterns and mask patterns, and a matching pattern read from the pattern matching memory and the byte assembly circuit. It has a matching circuit for signal reception by I, a mask calculation circuit for the mask pattern, and a matching result register, and the pattern matching memory stores matching patterns and mask patterns for each address block consisting of a plurality of bytes. The pattern matching circuit has a plurality of matching pattern/mask pattern pairs to be stored, and the pattern matching circuit has a counter for updating the address block and the received signal byte, and has a function of accessing the pattern matching memory based on the output of the counter. It is configured to perform a matching process with the matching pattern/mask pattern of each address block every time a 1-byte signal is received from the signal line.

[Industrial application field]

The present invention relates to a line monitoring device that transmits and receives information using a flag synchronous transmission method.

A connection configuration diagram of a line for transmitting and receiving digital information using the flag synchronous transmission method is shown in FIG. 5(a). In the figure, 21
is the processing unit of the host computer, 22 is the line control unit (DCU), and 23 is the line V! A terminal unit (DSU), 24 is a transmission terminal device, and 20 is a monitor device.

The line control device 22 and the line termination device 24 are connected by a transmitting/receiving line, and a flag-synchronized serial signal transmission system signal frame is transmitted and received through the transmitting/receiving line.

In order to monitor and check these signal frames, a monitor device 20 relay-connected to the signal line monitors them and performs signal frame verification processing.

This transmission system is often used in X25 and Na2CO3 common line signal systems. The signal frame structure of the flag synchronous transmission method is shown in FIG. 5(b).

In the figure, F indicates a flag pattern “011111
10" 8-bit signal. The CRC of the signal frame indicates a check code, and a 2-byte (16-bit) signal constitutes a frame check sequence. The signal frame consists of user information, and the monitor device In order to monitor specific patterns in the address (destination station specification) part and command (data type) part of the frame and check the signal type, calling party type, etc., we extract signals with specific information parts and Count the number of appearances.

[Conventional technology]

FIG. 6 shows a block diagram of a conventional monitor device. In the figure, 11 is a repeater, 12 is a signal receiving circuit, 13 is a DMA transfer circuit, 14 is a man-machine interface, 1
5 is a microprocessor MPU, 16 is a memory MEM,
17 is a display CRT, 1B is a keyboard, and 20 is a monitor device.

The signal receiving circuit 12 generally has the functions of assembling serially transmitted signals in bytes, detecting flags, removing zeros, and checking CRC, and extracts signal parts and performs DMA processing.
The signal is stored in the memory 16 through the transfer circuit 13.

To explain the monitoring method, FIG. 7 shows an example of setting conditions for matching signal frames. In the figure, ■ indicates a signal frame, ■ indicates a matching pattern, and ■ indicates a mask pattern.

The matching pattern ■ and the mask pattern ■ are stored in the memory 16 in advance.
The received signal frame is matched with the received signal frame. In the matching process of the conventional monitor device 20, the microprocessor (5) matches the received signal frame (2) transferred to the memory 16 with the verification pattern (2) and the mask pattern (2).

[Hardness to be solved by the invention] J.2 Conventional monitor devices have the advantage of being able to perform various types of verification by performing verification using a microprocessor, but when the line speed is high, It has the disadvantage that the number of matching patterns is limited.

In other words, if the processing time of 20//s is required to match 1 byte, the line speed is 641 (b/s) and the receiving interval of 1 byte is 12571 s, so it is possible to match only 6 patterns at most. Given the current situation, no significant performance improvement can be expected even with the use of high-performance microprocessors.

The present invention temporarily stores the received signal frame in memory,
After that, instead of checking using a microprocessor,
It is an object of the present invention to install hardware dedicated to matching processing so as to be able to perform masochining processing with a large number of matching patterns on one signal frame without any defects in matching processing.

[Means to solve the problem]

FIG. 1 shows the principle configuration diagram of the present invention. In the figure, 1 is a line relay receiving circuit, 2 is a flag detection circuit, 3 is a pattern matching circuit, 4 is a byte assembly circuit, 5 is an MA transfer circuit, 6 is a memory, and 7 is a microprocessor.

In the pattern matching circuit 3, 31 is a pattern matching memory, 32 is a munching circuit, 33 is a mask calculation circuit, 3
4 indicates a matching result register, and 35 indicates a counter.

The line relay receiving circuit 1 includes a flag detection circuit 2 for detecting a flag pattern of a received signal, a byte assembly circuit 4 for assembling a signal frame one byte at a time, and a pattern matching circuit 3 dedicated to frame pattern matching processing. The matching circuit 3 includes a pattern matching memory 31 that stores matching patterns and mask patterns, a matching circuit 32 between the matching pattern read from the pattern matching memory 31 and the signal reception byte from the high 1 assembly circuit 4; The pattern matching memory 31 has a mask calculation circuit 33 for calculating a mask pattern and a matching result register 34, and the pattern matching memory 31 stores a matching pattern and a mask pattern for each address block consisting of a plurality of bytes. The pattern matching circuit 3 also has a counter 35 for updating and receiving address blocks (updating February High 1-).
According to the output of the counter 35, the pattern matching memory 3
Configure to access 1.

Note that the counter 35 for accessing the memory is composed of two counters, one for counting the received signal pi1~, and the other for specifying the address block.

[Operation] When the flag detection circuit 2 detects a change from a flag pattern to a non-flag pattern, the pattern matching circuit 3 sequentially outputs the received signal byte, the matching pattern, and the first bye I of the mask pattern, and performs byte-by-byte matching. . The pattern matching memory 31 stores a plurality of matching patterns and mask patterns for each address block, and updates the address block counter for one received signal high 1 to read the first byte of each address block. Verification is performed, and when the verification of all blocks is completed, the received signal byte counter is updated by (+1).

Further, the matching results of each block are stored in the matching result register 34 for each matching pattern. The initial value of the matching result register 34 is 0, and it is 0 if there is a match in pattern matching.
If there is a mismatch, write 1. When the matching of one signal frame is completed, the matching result remains in the matching result register 34, and it can be determined whether each matching pattern is matched or not matched.

As described above, in the present invention, by performing matching processing by hardware, matching of 1 byte is performed once for one pattern.
It can be implemented in less than μs, and when the line speed is 64Kb/s (1 byte interval is 125 μs), the maximum
It is possible to match against multiple patterns.

〔Example〕

A block diagram of an embodiment of the monitor device is shown in FIG. In the figure, 1 to 7 are the same numbers as in the principle block diagram, 8 is a host interface circuit, 9 is a computer, and IO is a monitor device.

The monitor device 10 includes a line relay/reception circuit 1 that receives signals while relaying signal lines, a byte assembly circuit 4 that assembles pinto serial signals into bytes, and a flag detection circuit that detects flag patterns and identifies the start and end of a signal frame. Circuit 2, DMA that transfers signals assembled into bytes to memory 6
A transfer circuit, a pattern matching circuit 3 that compares the signal frame with a predetermined matching pattern, a memory 6 (having a signal frame reception buffer), a microprocessor 7, and an interface with the host computer 9 that controls the monitor device 10; It is constituted by a circuit 8.

FIG. 3 shows a block diagram of an embodiment of a pattern matching circuit which is a feature of the present invention. In the figure, a pattern matching memory 31 stores matching patterns and mask patterns. The matching pattern and the mask pattern each consist of 32 bytes, and there are 64 sets of them, and one signal frame is subjected to munching with the 64 matching patterns.

Pattern matching memory 31 is accessed by a 12-bit counter 35.

Assuming that the first byte of the signal frame is now received, the signal byte is input from the byte assembly circuit 4 to the reception buffer 36. Further, address 0 (#0 matching pattern) of the pattern matching memory 31 is read out, a comparison is made in the EOR circuit, and the result is stored in the matching buffer 3 . Next, the counter 35 (
+32), the #0 mask pattern is read out, the verification result and mask information are calculated, and the verification result register 3 is read out.
It is stored in 4.

Further, the counter is incremented by (+32), and matching processing with the #1 matching pattern and mask pattern is performed up to #63. After completing the 64 pattern comparisons, it waits for the reception of the second high I. When the second byte is received, the counter is incremented by (+1) and the second byte of each block in the pattern comparison memory 31 is read out. Thereafter, the matching process continues until the end flag of the signal frame is detected, and the final result remains in the matching result register 34. The flag detection circuit 2 notifies the microprocessor 7 of the end of a signal frame, and at the end of one signal frame, the microprocessor 7 reads out the value of the matching result register 34 of this circuit via the selector 38.

A tying chart of the pattern matching circuit of the above embodiment is shown in FIG. The figure shows when the first signal byte is received and when the second signal byte is received. , shows the relationship between the reading of matching patterns and mask patterns from pattern #0 to pattern #63, and storage in the matching buffer and matching register. (+1) and (+32) indicate the count value of the counter.

The pattern matching memory can be read within 250 ns, one pattern matching process can be performed within 1 μs, and 64 pattern matching is fully possible for a 641 b/s signal link.

〔Effect of the invention〕

In today's world of advanced communication control, there are many types of signal frames in a single signal link, and monitoring them requires matching many patterns, which is difficult to track with conventional processing technology. However, these problems can be solved by the pattern matching circuit of the present invention.

Although the present invention has the disadvantage of being higher in cost than the prior art, it significantly improves monitor performance and improves convenience in use.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the monitor device, FIG. 3 is a block diagram of a pattern matching circuit of the embodiment, and FIG. 4 is a timing chart of the embodiment. Figure 5 is a schematic diagram of the frame synchronization transmission system, Figure 6
The figure is a block diagram of a conventional monitor device, and FIG. 7 shows a standard example of signal frame matching conditions. In the figure, l is a line relay reception circuit, 2 is a flag detection circuit, 3 is a pattern matching circuit, 4 is a byte assembly circuit, 5,
13 is a DMA transfer circuit, 6.16 is a memory, 7.15 is a microprocessor, 8 is a host interface circuit,
9 is a computer, 10.20 is a monitor device, ], I
12 is a signal receiving circuit, 4 is a man-machine interface, 17 is a display, 18 is a keyboard, 121 is a processing device, 22 is a line control device, 23
is a line control device, 24 is a transmission terminal device, 31 is a pattern matching memory, 32 is a matching circuit, 33 is a mask calculation circuit, 34 is a general result register, 35 is a counter, 36
37 is a receiving buffer, 37 is a collation buffer, and 38 is a selector. O ■

Claims (3)

[Claims] (1) In monitoring signal frames in a flag-synchronized serial transmission system, the line relay receiving circuit (1) is equipped with a flag detection circuit (2) that detects the flag pattern of the received signal, and a pit assembly that assembles the signal frame one byte at a time. circuit (4), and a pattern matching circuit (3) dedicated to frame pattern matching processing, the pattern matching circuit (3) includes a pattern matching memory (31) that stores matching patterns and mask patterns, and a pattern matching circuit (31) that stores matching patterns and mask patterns; It has a matching circuit (32) between the matching pattern to be read and the signal received byte from the byte assembling circuit (4), a mask calculation circuit (33) with the mask pattern, and a matching result register (34). . A monitor device characterized in that each time a 1-byte signal is received from a signal line, it performs a matching process with a matching pattern/mask pattern of each address block. (2) The monitor device according to item 1, wherein the pattern matching memory (31) has a plurality of matching pattern/mask pattern pairs that store matching patterns and mask patterns for each address block consisting of a plurality of bytes. (3) The pattern matching circuit (3) has a counter (35) that updates address blocks and received signal bytes, and has a function of accessing the pattern matching memory (31) using the output of the counter (35). 2. The monitor device according to claim 1, comprising: