JPH033230A - Semiconductor vapor growth method - Google Patents
Semiconductor vapor growth methodInfo
- Publication number
- JPH033230A JPH033230A JP13577489A JP13577489A JPH033230A JP H033230 A JPH033230 A JP H033230A JP 13577489 A JP13577489 A JP 13577489A JP 13577489 A JP13577489 A JP 13577489A JP H033230 A JPH033230 A JP H033230A
- Authority
- JP
- Japan
- Prior art keywords
- growth
- pressure
- period
- semiconductor crystal
- crystal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
同じ組成であっても、特性を異にする半導体結晶層を成
長させるのに好適な半導体気相成長方法に関し、
半導体結晶層の減圧気相成長中に圧力を任意に変化させ
、特性が異なり、しかも、良質である半導体結晶層を効
率良く多層に積層できるようにすることを目的とし、
第一の半導体結晶層を減圧気相成長させる工程と、次い
で、該第一の半導体結晶層と特性を異にする第二の半導
体結晶層を前記減圧気相成長圧力よりも高い圧力で減圧
気相成長させて積層するに際し材料ガスの供給を遮断し
て反応室内を一旦真空排気する工程と、次いで、キャリ
ヤ・ガスを流して反応室を前記高い圧力状態としてから
材料ガスを流し第二の半導体結晶層を減圧気相成長させ
る工程とが含まれてなるよう構成する。[Detailed Description of the Invention] [Summary] This method relates to a semiconductor vapor phase growth method suitable for growing semiconductor crystal layers having different properties even though they have the same composition. The purpose of this process is to arbitrarily change the semiconductor crystal layer to efficiently stack multiple layers of semiconductor crystal layers having different characteristics and good quality. When a second semiconductor crystal layer having different properties from the first semiconductor crystal layer is deposited by vacuum vapor growth at a pressure higher than the vacuum vapor growth pressure, the supply of material gas is cut off and The structure includes the steps of once evacuation of the reaction chamber, and then a step of flowing a carrier gas to bring the reaction chamber to the high pressure state, and then flowing a material gas to grow a second semiconductor crystal layer in a reduced pressure vapor phase. do.
本発明は、同じ組成であっても、特性を異にする半導体
結晶層を成長させるのに好適な半導体気相成長方法に関
する。The present invention relates to a semiconductor vapor phase growth method suitable for growing semiconductor crystal layers having the same composition but different characteristics.
現在、基板に半導体結晶薄膜を多層に積層し、種々の機
能をもつ半導体装置を作成することが行われている。Currently, semiconductor devices having various functions are manufactured by laminating multiple layers of semiconductor crystal thin films on a substrate.
従って、品質が良好で、且つ、種々の特性をもつ半導体
結晶薄膜を効率良く成長させることができる技術が必要
とされる。Therefore, there is a need for a technique that can efficiently grow semiconductor crystal thin films of good quality and various characteristics.
一般に、シリコン系であると化合物半導体系であるとを
問わず、半導体装置を製造する場合、基板上に半導体結
晶層を成長させ、そこに素子を作り込むことが不可欠で
ある。In general, when manufacturing a semiconductor device, regardless of whether it is silicon-based or compound semiconductor-based, it is essential to grow a semiconductor crystal layer on a substrate and build elements therein.
従来、エピタキシャル成長の半導体結晶層を形成するに
は減圧気相成長方法が多用されていて、それを実施する
場合、反応室内の圧力は一定に保持されている。BACKGROUND ART Conventionally, a low pressure vapor phase growth method has been frequently used to form an epitaxially grown semiconductor crystal layer, and when this method is carried out, the pressure inside a reaction chamber is kept constant.
通常、半導体結晶層の特性、例えば、電気的特性、光学
的特性、面方位などは、その成長圧力に大きく依存する
。従って、従来の技術では、限られた特性の半導体結晶
層しか得られない。Usually, the properties of a semiconductor crystal layer, such as electrical properties, optical properties, and plane orientation, greatly depend on the growth pressure. Therefore, with conventional techniques, only semiconductor crystal layers with limited characteristics can be obtained.
そこで、成長中に圧力を変化させれば、様々な特性をも
つ半導体結晶層を多層に積層することができる。Therefore, by changing the pressure during growth, it is possible to stack multiple semiconductor crystal layers with various characteristics.
然しなから、現在、半導体結晶層の成長中に圧力を変化
させることは行われていない。その理由は、
(1) 圧力を下降させる場合には、あまり問題はな
いが、上昇させる場合には、急激に行うと成長ガスの澱
みが起き、界面に不都合な遷移層が形成されて成長に悪
影響を及ぼし、良質の半導体結晶層を成長させることが
できない。However, changing the pressure during the growth of a semiconductor crystal layer is not currently practiced. The reasons for this are: (1) There is not much of a problem when the pressure is lowered, but when it is raised rapidly, the growth gas stagnates and an unfavorable transition layer is formed at the interface, which impedes growth. This has an adverse effect and makes it impossible to grow a high-quality semiconductor crystal layer.
(2)前記(1)に述べた理由に依り、圧力の上昇及び
下降に時間を掛ける必要があり、成長時間が大変に長く
なる。(2) Due to the reason stated in (1) above, it is necessary to take time to increase and decrease the pressure, and the growth time becomes very long.
本発明は、半導体結晶層の減圧気相成長中に圧力を任意
に変化させ、特性が異なり、しかも、良質である半導体
結晶層を効率良く多層に積層できるようにする。The present invention makes it possible to arbitrarily change the pressure during the low-pressure vapor phase growth of a semiconductor crystal layer, thereby efficiently stacking multiple semiconductor crystal layers having different characteristics and high quality.
本発明に依る半導体気相成長方法に於いては、第一の半
導体結晶層(例えばp型GaAs薄膜21B)を減圧気
相成長させる工程と、次いで、該第一の半導体結晶層と
特性を異にする第二の半導体結晶層(例えばn型caA
s薄膜21A)を前記減圧気相成長圧力(例えば10”
’ (To r r) )よりも高い圧力(例えば10
(Torr))で減圧気相成長させて積層するに際し材
料ガス(例えばTMG及びASH3)の供給を遮断して
反応室(例えば反応室10)内を一旦真空排気する工程
と、次いで、キャリヤ・ガス(例えばH,)を流して反
応室を前記高い圧力状態としてから材料ガスを流し第二
の半導体結晶層を減圧気相成長させる工程とが含まれて
いる。In the semiconductor vapor phase growth method according to the present invention, there is a step of growing a first semiconductor crystal layer (for example, p-type GaAs thin film 21B) in a reduced pressure vapor phase, and then a step of growing a first semiconductor crystal layer (for example, a p-type GaAs thin film 21B) in a vacuum phase, and then having different characteristics from the first semiconductor crystal layer. a second semiconductor crystal layer (e.g. n-type caA
s thin film 21A) under the reduced pressure vapor phase growth pressure (for example, 10"
' (To r r) ) higher pressure (e.g. 10
(Torr)) When stacking layers by vapor phase growth under reduced pressure, the supply of material gases (for example, TMG and ASH3) is cut off and the inside of the reaction chamber (for example, reaction chamber 10) is once evacuated, and then the carrier gas is (for example, H) to bring the reaction chamber into the high pressure state, and then flowing a material gas to grow a second semiconductor crystal layer in a reduced pressure vapor phase.
前記手段を採ることに依り、成長圧力の上昇並びに下降
の時間を短縮することができ、また、反応室に材料ガス
の澱みを生ずることもなく、従って、半導体結晶層の減
圧気相成長中に圧力を任意に変化させ、特性が異なり、
しかも、良質である半導体結晶層を効率良く多層に積層
することが可能であって、低圧成長させた半導体結晶層
と高圧成長させた半導体結晶層との間に中間圧成長の半
導体結晶層が生成されるなどの虞もない。By adopting the above-mentioned means, it is possible to shorten the time for raising and lowering the growth pressure, and there is no stagnation of material gas in the reaction chamber. The pressure can be changed arbitrarily, the characteristics are different,
Moreover, it is possible to efficiently stack multiple high-quality semiconductor crystal layers, and an intermediate-pressure-grown semiconductor crystal layer is generated between the low-pressure-grown semiconductor crystal layer and the high-pressure-grown semiconductor crystal layer. There is no fear that it will happen.
第1図は本発明を実施するのに用いる半導体気相成長装
置の一例を説明する為の要部説明図を表している。FIG. 1 shows an explanatory view of essential parts for explaining an example of a semiconductor vapor phase growth apparatus used to carry out the present invention.
図に於いて、1並びに2はマス・フロー・コントローラ
、3並びに4はガス切り替えバルブ、5並びに6は排気
管、7並びに8はガス供給管、9はバルブ、10は反応
室、11はサセプタ、12はヒータ、13はウェハ、1
4は反応室マニホルド、15はニードル・バルブ、16
は真空ポンプ、17は排気管、18並びに19は材料ガ
スをそれぞれ示している。In the figure, 1 and 2 are mass flow controllers, 3 and 4 are gas switching valves, 5 and 6 are exhaust pipes, 7 and 8 are gas supply pipes, 9 is a valve, 10 is a reaction chamber, and 11 is a susceptor. , 12 is a heater, 13 is a wafer, 1
4 is a reaction chamber manifold, 15 is a needle valve, 16
17 is a vacuum pump, 17 is an exhaust pipe, and 18 and 19 are material gases, respectively.
第2図は本発明一実施例の成長シーケンスを説明する為
の線図である。FIG. 2 is a diagram for explaining the growth sequence of one embodiment of the present invention.
図に於いて、T1.T2.T3.T4はシーケンスの期
間を示している。尚、TI乃至T4が一サイクルを成し
ている。In the figure, T1. T2. T3. T4 indicates the period of the sequence. Note that TI to T4 constitute one cycle.
第1図に於いて、バルブ9を閉成し、真空ポンプ16を
作動すれば、反応室10は真空に排気される。In FIG. 1, the reaction chamber 10 is evacuated by closing the valve 9 and operating the vacuum pump 16.
今、反応室16内の圧力を高低二段に切り替えつつ、繰
り返し成長する場合について説明する。Now, a case will be described in which growth is repeated while changing the pressure in the reaction chamber 16 in two stages, high and low.
第2図から判るように、成長圧力シーケンスには、−サ
イクルに異なる四つのシーケンスが存在する。As can be seen from FIG. 2, there are four different growth pressure sequences in -cycles.
即ち、期間T1は高圧成長、期間T2は低圧成長、期間
T3は真空排気、期間T4は高圧成長である。That is, period T1 is high pressure growth, period T2 is low pressure growth, period T3 is vacuum evacuation, and period T4 is high pressure growth.
期間T1の高圧成長から期間T2の低圧成長に移行する
には別設の問題はないので、そのまま直ちに減圧する。Since there is no separate problem in transitioning from high-pressure growth in period T1 to low-pressure growth in period T2, the pressure is immediately reduced.
低圧成長から高圧成長に戻るには、そのままでは前記し
たような問題が起こるので、期間T3及びT4の二つの
シーケンスが必要である。従って、期間T2の低圧成長
が終了したならば、直ちに材料ガスを停止し、真空排気
を行うようにし、その後、キャリヤ・ガスの導入を行っ
て定常圧力になったところで材料ガスを導入するもので
あり、後はサイクルの繰り返しとなる。In order to return from low-pressure growth to high-pressure growth, two sequences of periods T3 and T4 are required, since the above-mentioned problems will occur if the growth is left as is. Therefore, once the low-pressure growth in period T2 is finished, the supply of material gas is immediately stopped and vacuum evacuation is performed, and then the carrier gas is introduced, and when the pressure reaches a steady state, the material gas is introduced. Yes, then the cycle repeats.
このようにして、成長圧力の上昇及び下降の為の時間を
短縮することができ、また、材料ガスが反応室16内に
滞留することもない。In this way, the time for increasing and decreasing the growth pressure can be shortened, and the material gas does not remain in the reaction chamber 16.
第3図は本発明を実施してGaAs薄膜を多層に積層し
た半導体ウェハの要部切断側面図を表している。FIG. 3 is a cross-sectional side view of a main part of a semiconductor wafer in which GaAs thin films are laminated in multiple layers according to the present invention.
図に於いて、20はGaAs基板、21Aはn型GaA
s薄膜、21Bはp型QaAs薄膜をそれぞれ示してい
る。In the figure, 20 is a GaAs substrate, 21A is an n-type GaA
s thin film and 21B indicate a p-type QaAs thin film, respectively.
ここで、n型caAsfjl膜21A及びp型GaAs
1膜21Bは共に厚さ100 〔人〕である。Here, the n-type caAsfjl film 21A and the p-type GaAs
Each film 21B has a thickness of 100 [people].
このウェハを得るには、次の条件で、第1図及び第2図
について説明した実施例と全く同様にして実施すると良
い。In order to obtain this wafer, it is preferable to conduct the process in exactly the same manner as in the embodiment described with reference to FIGS. 1 and 2 under the following conditions.
(11材料ガス
トリメチルガリウム(TMG: (CH3) 3G
a)アルシン(AsH3)
(2)■族と■族の比(A s Hs / TMG)V
/II[: 75
(3) キャリヤ・ガス
水素(H2)
(4)成長温度
T、:s5o (’C)
(5)成長圧力
p型(キャリヤ濃度は4 X 10” (C11弓)
)の場合: 10−’ (To r r)
n型(キャリヤ濃度は8X10”(ロー3〕)の場合:
LO(Torr〕
(6) シーケンスの期間
Tl:2〔秒〕
T2:2C秒〕
T3:1(秒〕
T4:2C秒〕
尚、この場合、真空とは10−’ (To r r)程
度を指すものとする。(11 Material Gas Trimethyl Gallium (TMG: (CH3) 3G
a) Arsine (AsH3) (2) Ratio of group ■ and group ■ (A s Hs / TMG) V
/II[: 75 (3) Carrier gas hydrogen (H2) (4) Growth temperature T, :s5o ('C) (5) Growth pressure p-type (carrier concentration is 4 X 10" (C11 bow)
): 10-' (To r r) In the case of n-type (carrier concentration is 8X10" (low 3)):
LO (Torr) (6) Sequence period Tl: 2 [seconds] T2: 2C seconds] T3: 1 (seconds) T4: 2C seconds] In this case, vacuum is about 10-' (Torr). shall point.
このようにして得られた第3図に見られるウェハでは、
pn界面が画然と分離していることを確認され、従って
、ドーピング超格子を形成するには好適と思われる。In the wafer obtained in this way and shown in FIG.
It was confirmed that the pn interface is clearly separated, and therefore it seems suitable for forming a doped superlattice.
本発明に依る半導体気相成長方法に於いては、成る特性
をもつ半導体結晶層を減圧気相成長させ、その半導体結
晶層と特性を異にする半導体結晶層を前記減圧気相成長
圧力よりも高い圧力で減圧気相成長させて積層するに際
し材料ガスの供給を遮断して反応室内を一旦真空排気し
、キャリヤ・ガスを流して反応室を前記高い圧力状態と
してから材料ガスを流し同じく高い圧力状態として前記
特性を異にする半導体結晶層を減圧気相成長させるよう
にしている。In the semiconductor vapor phase growth method according to the present invention, a semiconductor crystal layer having the characteristics of When stacking layers by vacuum vapor phase growth at high pressure, the supply of material gas is cut off, the reaction chamber is once evacuated, carrier gas is flowed to bring the reaction chamber to the high pressure state, and material gas is then flowed to the same high pressure. Semiconductor crystal layers having different characteristics as described above are grown in a reduced pressure vapor phase.
前記構成を採ることに依り、成長圧力の上昇並びに下降
の時間を短縮することができ、また、反応室に材料ガス
の澱みを生ずることもなく、従って、半導体結晶層の減
圧気相成長中に圧力を任意に変化させ、特性が異なり、
しかも、良質である半導体結晶層を効率良く多層に積層
することが可能であって、低圧成長させた半導体結晶層
と高圧成長させた半導体結晶層との間に中間圧成長の半
導体結晶層が生成されるなどの虞もない。By employing the above configuration, the time for increasing and decreasing the growth pressure can be shortened, and there is no stagnation of material gas in the reaction chamber. The pressure can be changed arbitrarily, the characteristics are different,
Moreover, it is possible to efficiently stack multiple high-quality semiconductor crystal layers, and an intermediate-pressure-grown semiconductor crystal layer is generated between the low-pressure-grown semiconductor crystal layer and the high-pressure-grown semiconductor crystal layer. There is no fear that it will happen.
第1図は本発明を実施するのに用いる半導体気相成長装
置の一例を説明する為の要部説明図、第2図は本発明一
実施例の成長シーケンスを説明する為の線図、第3図は
本発明を実施してGaAs薄膜を多層に積層した半導体
ウェハの要部切断側面図をそれぞれ表している。
図に於いて、l及び2はマス・フロー・コントローラ、
3及び4はガス切り替えバルブ、5及び6は排気管、7
及び8はガス供給管、9はバルブ、10は反応室、11
はサセプタ、12はヒータ、13はウェハ、14は反応
室マニホルド、15はニードル・バルブ、16は真空ポ
ンプ、17は排気管、18及び19は材料ガスをそれぞ
れ示している。FIG. 1 is an explanatory diagram of essential parts for explaining an example of a semiconductor vapor phase growth apparatus used to carry out the present invention, and FIG. 2 is a diagram for explaining the growth sequence of an embodiment of the present invention. 3 each shows a cutaway side view of a main part of a semiconductor wafer in which GaAs thin films are laminated in multiple layers according to the present invention. In the figure, l and 2 are mass flow controllers,
3 and 4 are gas switching valves, 5 and 6 are exhaust pipes, 7
and 8 is a gas supply pipe, 9 is a valve, 10 is a reaction chamber, 11
12 is a heater, 13 is a wafer, 14 is a reaction chamber manifold, 15 is a needle valve, 16 is a vacuum pump, 17 is an exhaust pipe, and 18 and 19 are material gases, respectively.
Claims (1)
半導体結晶層を前記減圧気相成長圧力よりも高い圧力で
減圧気相成長させて積層するに際し材料ガスの供給を遮
断して反応室内を一旦真空排気する工程と、 次いで、キャリヤ・ガスを流して反応室を前記高い圧力
状態としてから材料ガスを流し第二の半導体結晶層を減
圧気相成長させる工程と が含まれてなることを特徴とする半導体気相成長方法。[Claims] A step of growing a first semiconductor crystal layer in a reduced pressure vapor phase, and then growing a second semiconductor crystal layer having different characteristics from the first semiconductor crystal layer under the reduced pressure vapor growth pressure. When layering is performed by vacuum vapor phase growth at high pressure, the supply of material gas is cut off and the inside of the reaction chamber is once evacuated. Next, the reaction chamber is brought into the high pressure state by flowing carrier gas, and then the material gas is 1. A method for vapor phase growth of a semiconductor, comprising the step of growing a second semiconductor crystal layer in a low pressure vapor phase by depositing a second semiconductor crystal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13577489A JPH033230A (en) | 1989-05-31 | 1989-05-31 | Semiconductor vapor growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13577489A JPH033230A (en) | 1989-05-31 | 1989-05-31 | Semiconductor vapor growth method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033230A true JPH033230A (en) | 1991-01-09 |
Family
ID=15159545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13577489A Pending JPH033230A (en) | 1989-05-31 | 1989-05-31 | Semiconductor vapor growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033230A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5485244A (en) * | 1992-08-03 | 1996-01-16 | Star Micronics Co., Ltd. | Electrophotographic apparatus with freely openable upper and lower housings |
-
1989
- 1989-05-31 JP JP13577489A patent/JPH033230A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5485244A (en) * | 1992-08-03 | 1996-01-16 | Star Micronics Co., Ltd. | Electrophotographic apparatus with freely openable upper and lower housings |
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