JPH033251A - Sample holder - Google Patents

Sample holder

Info

Publication number
JPH033251A
JPH033251A JP1136950A JP13695089A JPH033251A JP H033251 A JPH033251 A JP H033251A JP 1136950 A JP1136950 A JP 1136950A JP 13695089 A JP13695089 A JP 13695089A JP H033251 A JPH033251 A JP H033251A
Authority
JP
Japan
Prior art keywords
sample
electrode layer
high frequency
layer
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1136950A
Other languages
Japanese (ja)
Inventor
Osamu Morita
治 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP1136950A priority Critical patent/JPH033251A/en
Publication of JPH033251A publication Critical patent/JPH033251A/en
Pending legal-status Critical Current

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To form a uniform electrified layer in the upper face of a sample and form a uniform film or perform uniform etching by separating an electrode layer into upper and lower layers with an insulating layer and applying DC voltage and high frequency to the upper and lower electrode layers respectively. CONSTITUTION:A sample mount 13 comprises upper and lower electrode layers 31 and 32 and an insulating layer 33 therebetween which are buried in an insulator 15 of ceramic or other materials and a high frequency application electrode rod 38 boring a cooling plate 11 is connected to the lower electrode layer 32. In adsorbing a sample 14, when a direct current is passed through a circuit the upper electrode layers 31a and 31b and the sample 14 are electrified to generate electrostatic power and the sample 14 is adsorbed to the sample mount 13. When high frequency is applied from an RF power source 38 to the lower electrode layer 32 and plasma is applied to form a film or perform etching, the upper face of the sample 14 is electrified negatively. Reactive gas ions are attracted to the electrified layer formed in the upper face of the sample 14 and a film is formed on the upper face of the sample 14 or the upper face of the sample 14 is etched.

Description

【発明の詳細な説明】 li上り五里旦y 本発明は試料保持装置、より詳細には静電吸着作用を利
用して試料を吸着保持する試料保持装置に関し、特に、
半導体集積回路の製造過程において、試料を高真空下に
おいて吸着保持する場合などに用いられる試料保持装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sample holding device, and more particularly, to a sample holding device that uses electrostatic adsorption to adsorb and hold a sample.
The present invention relates to a sample holding device used to hold a sample under high vacuum in the manufacturing process of semiconductor integrated circuits.

正米Ω弦1 例えば、電子サイクロトロン共鳴(ElectronC
yclotron Re5onancel を利用して
生成されるECRプラズマにより、試料の表面上に所望
の物質の薄膜を形成せしめるC V D lchemi
cal VaperDeposition)装置、ある
い゛は試料の表面上に微細な回路パ、ターンを形成せし
めるドライエツチング装置などの半導体集積回路の製造
装置等においては、前記試料を、高真空状態に維持され
た処理室内に保持するために、静電吸着力を利用する静
電チャック式の試料保持装置が広(用いられている。
For example, electron cyclotron resonance (ElectronC
C V D lchemi, which forms a thin film of a desired substance on the surface of a sample using ECR plasma generated using yclotron Re5onancel.
In semiconductor integrated circuit manufacturing equipment such as cal vapor deposition equipment or dry etching equipment that forms fine circuit patterns or patterns on the surface of a specimen, the specimen is subjected to processing that is maintained in a high vacuum state. Electrostatic chuck-type sample holding devices that utilize electrostatic adsorption force are widely used to hold samples indoors.

従来のこの種試料保持装置としては、一般に第4図に示
すような単極式の静電チャック構造が採用されている。
A conventional sample holding device of this type generally employs a monopolar electrostatic chuck structure as shown in FIG.

この単極式の静電チャックの構造は、基台(図示せず)
に冷却板11が載置され、この冷却板11の内部には冷
却液を循環させるための流路12が形成されている。こ
の流路12には外部から冷却液が導入、導出できるよう
に構成され、冷却板11の上方には試料台13がシリコ
ンゴム等の伝熱体(図示せず)を介して載置されており
、この試料台13の上部に試料14が載せられるように
なっている。試料台13は例えばセラミックなどから構
成される絶縁体15内部に電極層16が埋設された格好
で形成されており、この電極層16には冷却板11を貫
通して電極棒17が接続されている。電極棒17には直
流(DC)電源(図示せず)および高周波(RF)電源
(図示せず)が接続されている。
The structure of this monopolar electrostatic chuck consists of a base (not shown)
A cooling plate 11 is placed on the cooling plate 11, and a flow path 12 for circulating a cooling liquid is formed inside the cooling plate 11. The flow path 12 is configured so that a cooling liquid can be introduced and led out from the outside, and a sample stage 13 is placed above the cooling plate 11 via a heat transfer body (not shown) such as silicone rubber. A sample 14 is placed on the top of this sample stage 13. The sample stage 13 is formed with an electrode layer 16 embedded inside an insulator 15 made of ceramic or the like, and an electrode rod 17 is connected to the electrode layer 16 by penetrating the cooling plate 11. There is. A direct current (DC) power source (not shown) and a radio frequency (RF) power source (not shown) are connected to the electrode rod 17.

上記構造の試料保持装置の等価回路図を第5図に示す0
図中、試料14と電極層16との間にはコンデンサC1
が構成され、電極層16側にはDC電源18の正側およ
びRF電源19が接続されており、DC電源18および
RF電源19の他端は接地されている。DC電源18と
電極層16の間にはコイル20が介装されている。また
試料14側にはプラズマ・アシストまたは搬送アーム等
からなる、補助回路21が接続され、この補助回路21
の一端は接地されている。
An equivalent circuit diagram of the sample holding device with the above structure is shown in Figure 5.
In the figure, a capacitor C1 is connected between the sample 14 and the electrode layer 16.
The positive side of the DC power source 18 and the RF power source 19 are connected to the electrode layer 16 side, and the other ends of the DC power source 18 and the RF power source 19 are grounded. A coil 20 is interposed between the DC power source 18 and the electrode layer 16. Further, an auxiliary circuit 21 consisting of a plasma assist or a transfer arm is connected to the sample 14 side, and this auxiliary circuit 21
One end of is grounded.

ここで、吸着力は、印加電圧の2乗に比例し、絶縁層厚
さの2乗に逆比例する。
Here, the adsorption force is proportional to the square of the applied voltage and inversely proportional to the square of the thickness of the insulating layer.

以上のごとく構成された試料保持装置において、被吸着
物である試料14を吸着、離脱させる方法について説明
する。補助回路21としてプラズマ・アシストを用いる
場合、試料14を吸着、保持させるには、試料14を試
料台13の上面に載せ、DC電源18をONにするとと
もに、試料14の上面に短時間プラズマを照射する。1
i極層16は正の直流電圧により正に帯電するので試料
14下面は負に帯電しようとする。と同時にプラズマ照
射により、接地された補助回路21と試料14とがコン
デンサCIを介して導通され、試料14と電極層16と
の間に電界が発生する。このため、正負の電荷間の静電
気力により試料14は試料台13上に吸着、保持される
こととなる。試料を吸着させた後、RF電源をONにし
、成膜、エツチング等の処理を行なう。
In the sample holding device configured as described above, a method for adsorbing and detaching the sample 14, which is an object to be adsorbed, will be explained. When using plasma assist as the auxiliary circuit 21, in order to attract and hold the sample 14, place the sample 14 on the top surface of the sample stage 13, turn on the DC power supply 18, and apply plasma to the top surface of the sample 14 for a short time. irradiate. 1
Since the i-pole layer 16 is positively charged by the positive DC voltage, the lower surface of the sample 14 tends to be negatively charged. At the same time, due to the plasma irradiation, the grounded auxiliary circuit 21 and the sample 14 are electrically connected via the capacitor CI, and an electric field is generated between the sample 14 and the electrode layer 16. Therefore, the sample 14 is attracted and held on the sample stage 13 by the electrostatic force between the positive and negative charges. After adsorbing the sample, the RF power source is turned on and processes such as film formation and etching are performed.

成膜、エツチング等の処理において、直流電圧の印加だ
けでは試料14表面の電荷はプラズマにより中和されて
しまうが、高周波を印加しているので、この高周波の変
化に対応してたえず試料14と電極層16との間に充電
・放電が行なわれるようになり、試料14上面の電荷は
正負に交互に変化する。このため、試料14上面ではプ
ラズマ照射による正のイオンと電子(e−)が交互に引
き寄せられることになるが、イオンは電子に比べて非常
に質量が大きいため、イオンの速度は電子に比べて非常
に小さなものとなる。このため高周波の周波数が増加し
ていくとイオンはもはや電界の急速な変化についてゆけ
なくなり、試料14上面にはしだいに電子だけが蓄積さ
れ、試料14上面は負に帯電する。このため、成膜処理
またはエツチング処理を行なう場合には、反応ガスイオ
ンが試料14上面に形成された負の帯電による電界に引
き付けられ、試料14上面への入射方向が垂直に誘導さ
れるので、サイドエツチングのような不具合な現象が抑
制され、良好な回路パターンを形成することができる。
In processes such as film formation and etching, if only a DC voltage is applied, the charge on the surface of the sample 14 will be neutralized by plasma, but since a high frequency is applied, the charge on the sample 14 will be constantly changed in response to changes in this high frequency. Charging and discharging begin to occur between the sample 14 and the electrode layer 16, and the charge on the upper surface of the sample 14 changes alternately between positive and negative. Therefore, positive ions and electrons (e-) due to plasma irradiation are alternately attracted to the top surface of the sample 14, but since ions have a much larger mass than electrons, the speed of ions is lower than that of electrons. It will be very small. For this reason, as the frequency of the high frequency increases, the ions can no longer keep up with the rapid changes in the electric field, and only electrons gradually accumulate on the top surface of the sample 14, causing the top surface of the sample 14 to become negatively charged. Therefore, when performing a film forming process or an etching process, the reaction gas ions are attracted to the electric field due to the negative charge formed on the top surface of the sample 14, and the direction of incidence on the top surface of the sample 14 is guided vertically. Undesirable phenomena such as side etching are suppressed, and a good circuit pattern can be formed.

試料14を試料台13かも離脱させるには、DC電源1
8、RF電源19をOFFにし、プラズマを照射して試
料14と補助回路21とを導通させると、試料14に蓄
積されている電荷は接地されるため、前記静電気力によ
る吸着力は消失する。なお、試料14の吸着、保持は成
膜処理またはエツチング処理前に行なわれるのが通常で
あるが、これらの処理を施す際のプラズマ照射を利用し
てこれらの処理と同時に吸着・保持を行なうことも可能
である。
To detach the sample 14 from the sample stage 13, turn on the DC power supply 1.
8. When the RF power source 19 is turned off and plasma is irradiated to bring the sample 14 and the auxiliary circuit 21 into conduction, the charges accumulated in the sample 14 are grounded, and the adsorption force due to the electrostatic force disappears. Note that adsorption and retention of sample 14 are normally performed before film formation or etching treatment, but it is also possible to adsorb and retain sample 14 at the same time as these treatments by using plasma irradiation when performing these treatments. is also possible.

補助回路21として搬送アームを用いる場合、電極層1
6に直流電圧を印加するとともに接地されている搬送ア
ームを試料14に接触させると、試料14と電極層16
との間に電界が発生し、電極層16側には正の電荷が蓄
積される一方、試料14測には負の電荷が蓄積される。
When using a transport arm as the auxiliary circuit 21, the electrode layer 1
When a DC voltage is applied to the electrode layer 6 and the grounded transport arm is brought into contact with the sample 14, the sample 14 and the electrode layer 16
An electric field is generated between them, and positive charges are accumulated on the electrode layer 16 side, while negative charges are accumulated on the sample 14 side.

この正負の電荷による静電気力によって試料14は試料
台13上に吸着、保持される。その後、エツチング処理
等を開始する前に通常RF電源19をONにする。エツ
チング処理等の終了後試料14を試料台13かも離脱さ
せるには、DC電源18、RF電源19をOFFにし、
再び搬送アームを試料14に接触させると、試料14に
蓄積されている電荷は接地されている搬送アームによっ
て放電されるため、前記静電気力による吸着力は消失す
る。
The sample 14 is attracted and held on the sample stage 13 by the electrostatic force caused by the positive and negative charges. Thereafter, the RF power source 19 is normally turned on before etching processing or the like is started. To remove the sample 14 from the sample stage 13 after the etching process, etc., turn off the DC power supply 18 and the RF power supply 19.
When the transport arm is brought into contact with the sample 14 again, the electric charge accumulated on the sample 14 is discharged by the grounded transport arm, so that the adsorption force due to the electrostatic force disappears.

以上説明した通り単極式の静電チャックでは、試料14
と電極層16との間に電荷を蓄積することにより試料1
4を吸着、保持させる場合、及びこの蓄積された電荷を
放電させて試料14を離脱させる場合には、補助回路2
1が不可欠であった。
As explained above, with a monopolar electrostatic chuck, the sample 14
sample 1 by accumulating charge between the electrode layer 16 and
4, and when discharging this accumulated charge and detaching the sample 14, the auxiliary circuit 2
1 was essential.

また、補助回路21により試料14を吸着・離脱させる
場合、電荷の移動が円滑に行なわれにくいため、試料1
4の吸着に必要な静電気力を得るには時間がかかり単位
時間あたりの製造個数が少なくなるという欠点がある。
Furthermore, when the sample 14 is adsorbed and detached by the auxiliary circuit 21, it is difficult for the charge to move smoothly.
There is a disadvantage that it takes time to obtain the electrostatic force necessary for attracting No. 4, and the number of pieces manufactured per unit time is reduced.

また離脱時においても、補助回路21により試料14中
の電荷を接地させても残留電荷が多く、試料14は試料
台13に強く吸着された状態に維持されるため、搬送ア
ーム等で試料14を持ち上げようとしたとき試料14が
破損しやすい欠点がある。
Furthermore, even when detached, there is a large amount of residual charge even if the charge in the sample 14 is grounded by the auxiliary circuit 21, and the sample 14 remains strongly attracted to the sample stage 13. There is a drawback that the sample 14 is easily damaged when attempting to lift it.

このように、単極式の静電チャック構造を有する試料保
持装置では、補助回路21を形成する必要がある、吸着
・保持するのに時間がかかる、残留電荷により離脱時試
料が破損するおそれがある等の問題点があるため、単極
式の静電チャック構造に代わるものとして双極式の静電
チャック構造が開発されている。
As described above, in a sample holding device having a monopolar electrostatic chuck structure, it is necessary to form an auxiliary circuit 21, it takes time to attract and hold the sample, and there is a risk that the sample may be damaged when detached due to residual charge. Due to certain problems, bipolar electrostatic chuck structures have been developed as an alternative to monopolar electrostatic chuck structures.

この双極式の静電チャックは、第6図に示すように、電
極層が正の直流電圧が印加される電極層22と負の直流
電圧が印加される電極層23とに分離形成される一方、
双方の電極層22.23にはそれぞれ高周波(RF)が
印加されている。したがって、双極式の静電チャック構
造では、補助回路なしでも試料14を吸着・離脱させこ
とができ、しかも各電極層22.23に別々に直流電圧
な印加できることから、直流電源を切り換えれば簡単に
反転電圧を印加することができ、残留電荷な0にするこ
とができる等、補助回路21の有する種々の問題を解決
することができる。
In this bipolar electrostatic chuck, as shown in FIG. 6, the electrode layer is formed separately into an electrode layer 22 to which a positive DC voltage is applied and an electrode layer 23 to which a negative DC voltage is applied. ,
Radio frequency (RF) is applied to both electrode layers 22 and 23, respectively. Therefore, with the bipolar electrostatic chuck structure, it is possible to attract and detach the sample 14 without an auxiliary circuit, and since DC voltage can be applied to each electrode layer 22 and 23 separately, it is easy to change the DC power supply. Various problems with the auxiliary circuit 21 can be solved, such as being able to apply an inversion voltage to the auxiliary circuit 21 and reducing the residual charge to zero.

が ゛しようと る。is trying to.

上記のような双極式の静電チャック構造は、吸着に時間
がかかる、残留電荷により離脱時試料が破損されるおそ
れがある等の補助回路21を用いた単極式の静電チャッ
ク構造に右ける問題点を解決することができる。しかし
ながら、双極式の静電チャック構造では、試料14を吸
着させる際電極層22.23に高周波を印加すると、高
周波の導入経路のわずかの差によっても回路のインピー
慢スに変化が生じるために、二つの電極層22.23に
均等な高周波を印加するのが難しいという欠点があった
。この結果、高周波の印加により試料14上面に形成さ
れる帯電層の電荷分布が不均一になるため、試料14上
面に入射して(る反応ガスイオンの分布及び方向性にも
乱れが生じ、成膜処理またはエツチング処理により形成
されたパターンが不均一になってしまうという問題があ
った。
The bipolar electrostatic chuck structure described above is not suitable for the monopolar electrostatic chuck structure using the auxiliary circuit 21, as it takes time to attract the sample and there is a risk that the sample may be damaged when detached due to residual charge. problems that can be solved. However, in the bipolar electrostatic chuck structure, when high frequency is applied to the electrode layers 22 and 23 when adsorbing the sample 14, even a slight difference in the introduction path of the high frequency causes a change in the impedance of the circuit. There was a drawback that it was difficult to apply uniform high frequency waves to the two electrode layers 22 and 23. As a result, the charge distribution of the charged layer formed on the top surface of the sample 14 due to the application of high frequency becomes non-uniform, and the distribution and directionality of the reactant gas ions incident on the top surface of the sample 14 are also disturbed. There is a problem in that the pattern formed by film processing or etching processing becomes non-uniform.

本発明は上記のような問題点に鑑みなされたものであっ
て、双極式の静電チャックにおいて、試料台に分離形成
された同じ高さレベルの複数の電極層に高周波を均等に
印加でき、したがって半導体集積回路の製造において良
好なパターンを形成することができる試料保持装置を提
供することな目的としている。
The present invention has been made in view of the above-mentioned problems, and is capable of uniformly applying a high frequency to a plurality of electrode layers at the same height level formed separately on a sample stage in a bipolar electrostatic chuck. Therefore, it is an object of the present invention to provide a sample holding device that can form good patterns in the manufacture of semiconductor integrated circuits.

゛ るための 上記目的を達成するために本発明では、試料が載せられ
る試料台と該試料台内に埋設された電極層とを備えた試
料保持装置において、前記電極層が絶縁層を介して上下
2層で構成され、上層の電極層は分離形成されて直流電
圧が印加される一方、下層の電極層には高周波が印加さ
れるように構成されていることを特徴としている。
In order to achieve the above-mentioned object, the present invention provides a sample holding device comprising a sample stage on which a sample is placed and an electrode layer embedded in the sample stage, in which the electrode layer is connected via an insulating layer. It is characterized by being composed of two layers, an upper and a lower layer, and the upper electrode layer is formed separately and is applied with a DC voltage, while the lower electrode layer is configured so that a high frequency is applied.

1里 上記構成によれば、高周波は下層の電極層に伝導してか
ら上下の電極層間における略同条件の絶縁層を通過した
後複数の上層の電極層に印加される。すなわち、高周波
は複数の上層の電極層に別々に印加されるのではなく、
下層の電極層を介して複数の上層の電極層に同時的に印
加されるので、高周波は各上層の電極層に均等に伝導す
る。
According to the above configuration, the high frequency is conducted to the lower electrode layer, passes through the insulating layer having substantially the same conditions between the upper and lower electrode layers, and is then applied to the plurality of upper electrode layers. In other words, the high frequency is not applied to multiple upper electrode layers separately;
Since the high frequency waves are simultaneously applied to a plurality of upper electrode layers via the lower electrode layer, the high frequency waves are equally conducted to each upper electrode layer.

寒土舅 以下、本発明にかかる試料保持装置の実施例を図面に基
づいて説明する。なお、従来例と同一構造の部分につい
ては同一の符合を付すこととする。
Embodiments of the sample holding device according to the present invention will be described below with reference to the drawings. Note that parts having the same structure as those of the conventional example are given the same reference numerals.

試料保持装置における静電チャックの構造は、第1図に
示すように、基台(図示せず)に冷却板11が載置され
ており、この冷却板11の内部には冷却液を循環させる
ための流路12が形成されている。この流路12には外
部から冷却液が導入、導出できるように構成されている
。冷却板11の上方には試料台13がシリコンゴム等の
伝熱体(図示せず)を介して載置されており、この試料
台13の上部に試料14が載せられるようになっている
。試料台13は例えばセラミックなどから構成される絶
縁体15内部に上下2層の電極層31.32が絶縁層3
3を介して埋設された格好で形成されており、下層の電
極層32には冷却板11を貫通する高周波印加用の電極
棒38が接続されている。上層の電極層31は平面視に
おいて半円形状の2枚の電極層31a、31bに分離形
成され、それぞれ直流電圧印加用の電極棒34.34が
冷却板11および下層の電極層32を貫通して接続され
ている(第2図)。
As shown in FIG. 1, the structure of the electrostatic chuck in the sample holding device is that a cooling plate 11 is placed on a base (not shown), and a cooling liquid is circulated inside the cooling plate 11. A flow path 12 is formed for this purpose. This flow path 12 is configured so that a cooling liquid can be introduced into and led out from the outside. A sample stage 13 is placed above the cooling plate 11 via a heat transfer member (not shown) such as silicone rubber, and a sample 14 is placed on top of this sample stage 13. The sample stage 13 has two upper and lower electrode layers 31 and 32 inside an insulator 15 made of ceramic or the like, and an insulating layer 3.
An electrode rod 38 for high frequency application that penetrates through the cooling plate 11 is connected to the lower electrode layer 32. The upper electrode layer 31 is formed separately into two semicircular electrode layers 31a and 31b in plan view, and electrode rods 34 and 34 for applying a DC voltage penetrate through the cooling plate 11 and the lower electrode layer 32, respectively. (Fig. 2).

上記試料保持装置の等価回路図を第3図に示す。図中、
下層の電極層32にはRF電源19が接続されており、
下層の電極層32は上層の電極層31a、31bとの間
でコンデンサC2、C4を構成し、上層の電極層31a
、31bは試料14との間でコンデンサC,,、C,を
構成している。左側のコンデンサC2,C,はそれぞれ
コイル20を介してDC電源35の正側に接続され、右
側のコンデンサC4、Csそれぞれコイル20を介して
DC電源36の負側に接続されており、DC電源35.
36はスイッチ37.37により左右の接続先のコンデ
ンサC、、C,とコンデンサC4、C1との切り換えが
できるようになっている。RF電源19およびDC電源
35.36の一端は接地されている。
FIG. 3 shows an equivalent circuit diagram of the sample holding device. In the figure,
An RF power source 19 is connected to the lower electrode layer 32,
The lower electrode layer 32 forms capacitors C2 and C4 with the upper electrode layers 31a and 31b, and the upper electrode layer 31a
, 31b constitute a capacitor C, , C, with the sample 14. The capacitors C2, C, on the left side are each connected to the positive side of the DC power supply 35 via the coil 20, and the capacitors C4, Cs on the right side are each connected to the negative side of the DC power supply 36 via the coil 20. 35.
36 is designed to be able to switch between the left and right connected capacitors C, , C, and the capacitors C4 and C1 by switches 37 and 37. One ends of the RF power source 19 and the DC power sources 35 and 36 are grounded.

試料14を吸着させる場合、この回路に直流電流を流す
と、上層の電極層31a、31bと試料14とが帯電し
て静電気力が発生し、試料14は試料台13に吸着され
る。RFit源38から下層の電極層32に高周波をか
けると、高周波はコンデンサC2、C4さらにはC3、
Csを介して試料14に伝播する。この印加された高周
波の変化に対応して試料14上面には正負の電荷が交互
にあられれるが、成膜処理またはエツチング処理のため
にプラズマ照射を行なった場合1反応ガスイオンと電子
(e−)のうち周波数の激しい変化に対応できる電子だ
けが試料14上面に蓄積され、試料14上面は負に帯電
する。この試料14上面に形成された帯電層に反応ガス
イオンが引き付けられ、試料14上面に成膜またはエツ
チングが施される。
When the sample 14 is to be attracted, when a direct current is passed through this circuit, the upper electrode layers 31a, 31b and the sample 14 are charged, an electrostatic force is generated, and the sample 14 is attracted to the sample stage 13. When a high frequency is applied from the RFit source 38 to the lower electrode layer 32, the high frequency is applied to the capacitors C2, C4, C3,
It propagates to the sample 14 via Cs. Positive and negative charges are alternately generated on the upper surface of the sample 14 in response to changes in the applied high frequency, but when plasma irradiation is performed for film formation or etching, one reaction gas ion and electron (e- ), only those electrons that can respond to drastic changes in frequency are accumulated on the upper surface of the sample 14, and the upper surface of the sample 14 becomes negatively charged. Reactive gas ions are attracted to the charged layer formed on the upper surface of the sample 14, and a film is formed or etched on the upper surface of the sample 14.

試料14を離脱する場合、DC電源35.36のスイッ
チ37.37を切り換えることにより反転電圧を印加す
ると、コンデンサC2、C、、C,、Csに蓄積されて
いる電荷は放電され、吸着力は消失する。
When detaching the sample 14, when a reverse voltage is applied by switching the switch 37.37 of the DC power supply 35.36, the charges accumulated in the capacitors C2, C, , C, , Cs are discharged, and the adsorption force is reduced. Disappear.

以上説明したとおり本実施例では、高周波は上層の電極
層に別々に印加されるのではなく、下層の一つの電極層
32を介して上層の電極層31a、31bに同時に印加
されるので、高周波を各上層の電極層31a、31bに
均等に伝導させることができる。したがって、試料14
に印加される高周波も均等になるため、試料14上面に
形成される帯電層の電荷分布も均一になり、試料14上
面に衝突する反応ガスイオンの分布状態及び入射方向も
全面にわたり均一的に誘導され、成膜処理またはエツチ
ング処理により形成される回路パターンを均一なものに
することが可能になる。
As explained above, in this embodiment, the high frequency is not applied to the upper electrode layers separately, but is simultaneously applied to the upper electrode layers 31a and 31b via one lower electrode layer 32. can be uniformly conducted to each upper electrode layer 31a, 31b. Therefore, sample 14
Since the high frequency applied to the sample 14 becomes uniform, the charge distribution of the charged layer formed on the top surface of the sample 14 becomes uniform, and the distribution state and incident direction of the reactive gas ions colliding with the top surface of the sample 14 are uniformly guided over the entire surface. As a result, it becomes possible to make the circuit pattern formed by the film forming process or the etching process uniform.

なお、上記した実施例では上層の電極層が二つに分離形
成された場合を示したが、上層の電極層は二つに限られ
るものではなく、三つ以上の複数個であっても差し支え
ない。
In addition, although the above-described embodiment shows a case where the upper electrode layer is formed separately into two, the number of upper electrode layers is not limited to two, and may be three or more. do not have.

及肌五盈玉 以上の説明により明らかなように、本発明にかかる試料
保持装置にあっては、試料が載せられる試料台と該試料
台内に埋設された電極層とを備えた試料保持装置におい
て、前記電極層が絶縁層を介して上下2層で構成され、
上層の電極層は分離形成されて直流電圧が印加される一
方、下層の電極層には高周波が印加されるように構成さ
れている。
As is clear from the above description, the sample holding device according to the present invention includes a sample stage on which a sample is placed and an electrode layer embedded in the sample stage. , the electrode layer is composed of upper and lower layers with an insulating layer interposed therebetween,
The upper electrode layer is formed separately and is configured to be applied with a DC voltage, while the lower electrode layer is configured to be applied with a high frequency.

したがって、複数の電極層への直流電圧の印加により、
単極式の静電チャック構造の欠点を除去できながら、し
かも高周波は二つの上層の電極層に別々に印加されるの
ではなく、下層の一つの電極層を介して両層同時に印加
されるので、複数の上層の電極層から試料に印加される
高周波を均等なものにすることができる。この結果、高
周波の印加により試料上面に均一に形成された帯電層に
より反応ガスイオンを試料全面にわたり均一に入射させ
ることができるため、成膜処理またはエツチング処理に
より形成される回路パターンを均一なものにすることが
可能になる。
Therefore, by applying a DC voltage to multiple electrode layers,
While the drawbacks of the monopolar electrostatic chuck structure can be eliminated, the high frequency is not applied to the two upper electrode layers separately, but is applied simultaneously to both layers through a single lower electrode layer. , it is possible to equalize the high frequency waves applied to the sample from the plurality of upper electrode layers. As a result, the charged layer uniformly formed on the top surface of the sample by applying high frequency waves allows reactive gas ions to be incident uniformly over the entire surface of the sample, resulting in a uniform circuit pattern formed by film formation or etching. It becomes possible to

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明にかかる試料保持装置の実施例を示す概
略断面図、第2図は第1図におけるA−A線断面図、第
3図は同装置の等価回路図。 第4図は従来の単極式の静電チャック構造を有する試料
保持装置を示す概略断面図、第5図は同装置の等価回路
図、第6図は双極式の静電チャック構造を有する試料保
持装置の等価回路図である。 13・・・試料台、14・・・試料、19・・・RF電
源、31.31a、31b・・・上層の電極層、32・
・・下層の電極層、33・・・絶縁層、35.36・・
・DC電源
FIG. 1 is a schematic sectional view showing an embodiment of the sample holding device according to the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is an equivalent circuit diagram of the same device. Fig. 4 is a schematic cross-sectional view showing a conventional sample holding device having a monopolar electrostatic chuck structure, Fig. 5 is an equivalent circuit diagram of the same device, and Fig. 6 is a sample holding device having a bipolar electrostatic chuck structure. FIG. 3 is an equivalent circuit diagram of the holding device. 13... Sample stage, 14... Sample, 19... RF power source, 31. 31a, 31b... Upper electrode layer, 32...
...Lower electrode layer, 33...Insulating layer, 35.36...
・DC power supply

Claims (1)

【特許請求の範囲】[Claims] 試料が載せられる試料台と該試料台内に埋設された電極
層とを備えた試料保持装置において、前記電極層が絶縁
層を介して上下2層で構成され、上層の電極層は分離形
成されて直流電圧が印加される一方、下層の電極層には
高周波が印加されるように構成されていることを特徴と
する試料保持装置。
In a sample holding device comprising a sample stage on which a sample is placed and an electrode layer embedded in the sample stage, the electrode layer is composed of two layers, upper and lower, with an insulating layer interposed therebetween, and the upper electrode layer is formed separately. A sample holding device characterized in that it is configured such that a DC voltage is applied to the lower electrode layer, while a high frequency wave is applied to the lower electrode layer.
JP1136950A 1989-05-30 1989-05-30 Sample holder Pending JPH033251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1136950A JPH033251A (en) 1989-05-30 1989-05-30 Sample holder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1136950A JPH033251A (en) 1989-05-30 1989-05-30 Sample holder

Publications (1)

Publication Number Publication Date
JPH033251A true JPH033251A (en) 1991-01-09

Family

ID=15187303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1136950A Pending JPH033251A (en) 1989-05-30 1989-05-30 Sample holder

Country Status (1)

Country Link
JP (1) JPH033251A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496221A (en) * 1990-08-03 1992-03-27 Matsushita Electric Ind Co Ltd Semiconductor manufacturing equipment and its manufacturing method
JPH06326177A (en) * 1993-05-17 1994-11-25 Tokyo Electron Ltd How to remove the object
US5521790A (en) * 1994-05-12 1996-05-28 International Business Machines Corporation Electrostatic chuck having relatively thick and thin areas and means for uniformly cooling said thick and thin areas during chuck anodization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0496221A (en) * 1990-08-03 1992-03-27 Matsushita Electric Ind Co Ltd Semiconductor manufacturing equipment and its manufacturing method
JPH06326177A (en) * 1993-05-17 1994-11-25 Tokyo Electron Ltd How to remove the object
US5521790A (en) * 1994-05-12 1996-05-28 International Business Machines Corporation Electrostatic chuck having relatively thick and thin areas and means for uniformly cooling said thick and thin areas during chuck anodization

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