JPH0332873A - Electronics - Google Patents

Abstract

PURPOSE:To provide an electronic equipment of simple structure which is capable of general use and is easy to assemble by providing a control device which latches information on the drive of a light-emitting element and information on the selection of each switching element for latch of the operating status of the switching element in the time-dividing mode. CONSTITUTION:A printer has a control panel for local control of paper feed instead of control by a host device. A connector 27 latches and outputs various kinds of signal through six signal lines. In addition, the printer has seven switches 18 to 24 and LED 9 and LEDs 10 to 17 in seven segments. Data are latched into and output from these switches and LEDs through a single latched shift register 25. These three groups are controlled respectively in the time dividing mode. Therefore, the latch of a signal into the main frame and the output of the signal from the frame can be achieved only through six signal lines, if many element wires are installed Eight output terminals of the shift register 25 are connected to seven segments LEDs 9 and four LEDs 10 to 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device, and particularly to an electronic device having an operation panel composed of a plurality of light emitting elements and switch elements.

[Prior Art] Conventionally, there has been known a technique for providing a user interface in various electronic devices using a light emitting element such as an LED and a switch such as a push button switch.

In the operation panel composed of light emitting elements and switches as described above, the light emitting elements whose emission should be controlled and the switches whose data should be inputted have signal lines equal to the total number, and power lines or ground lines to drive them. is connected to the control device of the device, and the main body control device lights up the light emitting elements by controlling each of the above-mentioned individual signal lines, and also captures switch press information.

[Problems to be Solved by the Invention] However, in the conventional structure as described above, the number of light emitting devices and switches corresponds to the number of signal lines for driving and detecting them. When expanding the number of signal lines, the number of signal lines increases accordingly, causing the following problems.

First, it is necessary to add input or output ports to the main body control device that controls the light emitting elements and switches. In addition, by increasing the number of light-emitting elements and switches, the number of signal lines increases accordingly, making it easier to route cables.
Safety, assembly process, assembly efficiency, etc. will need to be reconsidered.

Furthermore, if the number of light-emitting elements and switches differs, the circuit will have a completely different structure, so if you create multiple types of devices with different numbers of light-emitting elements and switches, parts such as circuit boards or control software such as the main body control section will be incompatible.

An object of the present invention is to solve the above problems and provide an electronic device having a simple structure, excellent versatility, and an easy-to-assemble operation panel.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, in an electronic device having an operation panel composed of a plurality of light emitting elements and switch elements, driving information of the light emitting elements, In order to input the operation state of the switch elements, selection information for selecting each switch element is input in a time-sharing manner from the main control section of the device, and the driving of the light-emitting element and the switching element are performed in a time-sharing manner based on the input drive information or selection information. A configuration is adopted that includes a control means for inputting the operating status.

[Function] According to the above configuration, the number of signal lines for signal input/output can be reduced because the driving of the light emitting element and the input of the operation state of the switch element are performed in a time-sharing manner.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the structure of a printer device as an example of equipment employing the present invention.

The illustrated printer 1 has a printer engine (mechanism) 4 configured based on various recording output methods such as an inkjet method and a laser beam method. Therefore, the recording operation is performed through control.

The power source of the device is composed of a switching power supply, etc. The device host device 8 is composed of a personal computer or a word processor, and is connected to the controller 5 by a connector 7. The controller 5 and the host device 8 input and output data based on various interface standards for serial or parallel data transmission.

The printer engine 4 has a carriage 2. This carriage device 2 is equipped with a recording head compatible with various recording methods, and performs a recording operation in a predetermined method by scanning a recording medium such as paper.

The printer 1 shown in FIG. 1 has an operation panel 3 for performing local control such as paper feeding without being controlled by the host device 8. The panel 3 has switches for directly causing the printer engine 4 to perform various operations such as paper feed, home feed, test printing, etc., as well as LEDs and 7-segment LEDs for displaying the operation status or operation mode of the switches. (The device will be described later), and is connected to the printer engine 4 via a connector 27.

Figure 2 shows the structure of panel 3 in Figure 1 in detail. The connector 27 inputs and outputs each f[ number through the six signal lines shown in the figure. Two of them are a power line (VCC) and a ground line (G) for supplying power from the printer engine 4 side.
ND).

The power line vCC supplies an output voltage of 5V to each part of the panel. Panel 3 has seven switches 18 to 24 (SW6 to SW
0), a 7-segment LED 9, and LEDIO to 17 for displaying various operations and modes.

Data input/output to these switches and LEDs is as follows:
This is done via a single shift register 25 with a latch. Switches 18 to 24, 7 segment LED 9, LED
The three groups numbered 10 to 17 are controlled in a time-sharing manner. Therefore, despite the large number of elements, signal output to and from the main body can be performed using only six signal lines (actually four excluding the power line) of the connector 27.

Further, the structure shown in FIG. 2 will be explained in detail.

Shift register 25 has eight output signal lines, each of which is connected to one end of the terminals of switches 18-24 via diodes D18-D24. Further, all contacts on the opposite side of the switch 18 are commonly connected to a signal line PANSW connected to the connector 27. This signal line PANSW is for sequentially outputting the output of any one of the switches 18 to 24 to the printer engine 4 side.

Further, the 8-tree output of the shift register 25 is also connected to the 7-segment LED 9 and the four LEDIO-17. That is, the eight output lines are first connected to the seven segment LED 9 via resistors R2-R9. The 7-segment LED 9 lights up 7 segments according to the combination of voltages at the output points of the resistors R2-R9, and displays numbers or alphabets.

The output points of the resistors R2-R9 are further connected to the cathodes of LEDIO-17 via resistors R11-R17 and resistor RIO. 9 7 segment LEDs and 8 L
Power supply to EDIO~17 is provided by transistor TRI.
, TR2. transistor T
The output of RI and TFt2 is added to the power supply voltage, and its pace is controlled by the decoder 26.

The decoder 26 is a signal line PAN accommodated in the connector 27.
S r and PANLD are input and decoded to selectively turn on either transistor TRI or TR2. Signal line PANLD is 7 segment LED9
Or it is used to select any of the eight LEDs 10-17.

The signal line PANSI is used to serially input drive information for lighting up the LEDIO-17 and switch selection information for inputting operation information for the switches 18-24.

The signal line PA is connected to the serial input terminal of the shift register 25.
A serial signal of NSI is input. Data is also shifted by the clock PANS supplied from the printer engine.
Controlled by WK.

FIG. 3 shows four signals other than the power line accommodated in the connector 27 of FIG. 1, PANSWK, PANS■, PANLD,
The timing of PANSW is shown. Note that in the following explanation, the * appended to the sign of the signal indicates negative logic. Third
The timing chart shown in the figure is composed of six sections aNf, and these six sections constitute one cycle of control.

First, in section a, data for lighting LEDIO-17 is transferred to the shift register 25.

For transfer data, lighting corresponds to high level and turning off corresponds to low level, and 8 bits are transferred using the signal line PANSI. Each data is clocked by shift register 25.
0 section a shifted and latched by the rising edge of K
~e is the signal line PANS to take in the switch output
W may be either high level or low level, but
In section a, the signal line PANLD is at low level (LED9
10 to 17) is set to high level.

Subsequently, in the section, LEDIO~17 is turned on. At this time, the signal line PANLD is set to low level, and the decoder 2
6 and LEDIO~17 via transistor TR2
are selected at the same time. Since each bit transferred in section a is latched in the output of the shift register 25, the LED corresponding to the bit to which the transfer data is set is
Any one of O to 17 is lit. It is assumed that the shift register 25 outputs lighting as a low level.

Next, in section C, data is transferred in the same way as in section a, but
The data transferred at this time is drive data for the 7-segment LED 9. This 8-pit data is transferred in the same way as in section a.

In section d, the 7-segment LED 9 is turned on based on the data transferred in section C. At this time, the signal line PANS
I is held at a low level, and decoder 26 selects 7-segment LED 9 via transistor TRI. At this time, the clock PANSCK is held at a high level as in the interval.

In section e, 8-bit low level data is sent to the signal line PANS in preparation for data acquisition of switches 18 to 24 in section f.
I and clear the shift register 25.

After this, the signal line PANLD is held at a high level, and the clock PANSCK becomes a pulse having a predetermined clock frequency.

At the beginning of section f, one bit of high-level data is input to the shift register 25 through the signal line PANSI.

This high level data is sequentially shifted in synchronization with the clock PANSCK, and appears in order at eight output terminals of the shift register 25. This causes diodes 018-2
4, one end of the switches 18 to 24 is sequentially brought to a low level, thereby selecting each switch.

In section f, if the signal line PANSW is pulled up to the power supply voltage on the printer engine 4 side, eight pits of serial data corresponding to the pressed states of the switches 18 to 24 can be taken in via the signal line PANSW. This data can be captured at appropriate timing on the printer engine side using a serial/parallel shift register, latch, or the like.

According to the above configuration, a large number of switch elements and two systems of LEDs can be controlled by at most four signal lines.

It is quite possible for one cycle constituted by sections a to f in FIG. 3 to last several ms to several tens of ms at most, and the user does not perceive that the switches and LEDs are controlled in a time-sharing manner.

Further, according to the above configuration, by controlling the length of sections d and d as desired, the 7-segment LED during the control cycle can be controlled as desired.
9 or the amount of lighting light of LEDIO to 17 can be changed. The length of this section bld can be set by adjusting the four signal lines shown in FIG. 3 using a control circuit as described below.

Figures 4 and 5 contain the four signals (PAN) in Figures 2 and 3.
SCK, PANSI, PANLD% PANS
This circuit is included as an internal circuit of the printer 1 excluding the printer engine 4 or the panel 3.

FIG. 4 shows a circuit that generates a signal PANSI for transferring LED lighting data and switch selection data.

Numbers 29 and 30 in Fig. 4 are 7 segment LEDs, respectively.
This is a latch that latches 8-bit data for driving LEDs 9 and LEDs 10 to 17, respectively. IDATA for lighting the LED or selecting the switch is latched in 8 bits from the printer engine 4 or the controller 5 in latches 29 and 30.

Printer engine 4 or controller 5 receives signal LD1
Latch 2 for 7 segment LED via 2 or 13
9 or the latch 30 for LEDIO-17.

Which output of latch 29 or 30 is used is selected by multiplexer 51.52. The 8-bit data selected by the multiplexers 51 and 52 is input to the parallel/serial shift register 53,
Converted to serial data.

The output of the parallel/serial shift register 53 is output to the signal line PANS1 via the gates 31 to 33.38. Gates 31 to 33 are for determining signal levels in sections b and d.

The gate 38 is a negative logic OR gate, and its information is output to a low level active (like a gate).

First, when the NAND gate 31 is selected by the signal PANS ISEL (generated by the circuit shown in FIG. 6, which will be described later) in sections a and c, the output of the parallel/serial shift register 53 is output as is.

Further, in the section 6% d, a high level (or low level) is outputted according to the level of the signal PNDISP inputted to one input terminal of the OR gate 32 (negative logic). The signal PNDISP is for instructing the LED 9 and the 7-segment LEDs 10 to 17 to be lit.

Further, 1-bit data in section f is formed by a signal PANSWS I output from the printer engine 4 and input via the inverter 33.

FIG. 5 shows a circuit that generates the signal PANLD of FIG. The clock PANCK is input to the clock terminals of counters 58 and 59, and the output of counter 1 is input to the J terminal of JK flip-flop 28. A clock PANCK is input to the clock input of the JK flip-flop 28, and the output of the counter 59 is inverted by an inverter 62 and input to the K input. The inverted output of JK flip-flop 28 enables counter 58 and resets counter 59 via inverter 61.

The output Q of the JK flip-flop 28 is input to the data input terminal of the D flip-flop 63.

The preset terminal of the D flip-flop 63 is pulled up to high level, and the clock input is the clock PANC.
K is input. The input/output signals of the D flip-flop 63 are input to a negative logic OR gate 92, and the signal PANL
D (negative logic in this figure) is formed. Signal PANL
D becomes low level when either one or both of the input and output signals of flip-flop 3 is low level;
If both are at high level, they are controlled to high level.

In the structure of FIG. 5, when the counter 58 reaches a predetermined value, J
The K flip-flop 28 operates, the counter 58 that outputs a low level from its inverted output stops, and the counter 59 starts counting.

The counting period of this counter 59 corresponds to section b%d in FIG.
2, and a low level signal PANLD is output from the output terminal of the D flip-flop 63. At the start point of the section b%d, the clock PANSCK is stopped via a path not shown, and the signal PANLD is controlled to a low level, so that the shift register 25 in FIG.
The data is latched. At this time, LEDs 10 to 17 or 7 segment LED 9 are lit based on the data.

When the counter 59 that determines the length of period 6% d reaches a predetermined value, a low level is input to the input of the JK flip-flop 28, the JK flip-flop 28 is inverted, the counter 59 is reset, and the counter 58 is selected again. to form a data transfer period.

In order to control the length of section b%d as desired, a circuit as shown in FIG. 6 can be used. Reference numeral 71 in Fig. 6
．． Reference numeral 72 denotes a counter element constituting the counter 59 in FIG. 5. First, the counter 72 is activated by an overflow carry of the counter 71 that counts the lower digits, and the upper digits are counted.

The gate circuit 80 in FIG. 6 is for determining whether or not the output of the counter 72 matches the 3-bit data corresponding to the length of the desired section (d) latched by the control system in the latch 34. It is.

By changing the 3-bit data latched in the latch 34 as desired, a signal can be input to the terminal of the JK flip-flop 28 at a desired timing. Therefore, the brightness of the LED perceived by the user can be controlled as desired according to the software by forming sections d, that is, the lighting period of the LED, of a desired length.

This perceived amount of light can be controlled by, for example, 7 segment L
It can be used to match the lighting intensity of ED9 and LEDIO~17. For example, a regular LED has more light than a 7-segment LED, so a 7-segment LED
By fixing the lighting time of D9 and controlling the lighting time of LEDIO to 17 to be short, the perceived light amount can be made equal.

Note that the NOR gate 91 in FIG. 6 is connected to the signal PA in FIG.
It forms NS I SEL, and is controlled to high level only when both the input and output signals of D flip-flop 63 are low level.

The above structure can also be modified as shown in FIG. This embodiment is an example in which the number of signal lines to be accommodated in the connector 27 is further reduced by one tree to five. In this embodiment, the signal line PANLD used in FIG. 2 is omitted,
The clock PANSCK is used as a latch signal for the shift register 25.

FIG. 8 shows a timing chart for the circuit of FIG. 7. In sections aC, e'f' of FIG. 8, the same operation as in the above embodiment is performed, but in b' and d', where the LEDs are lit, the low level is used to latch the shift register 25 using the clock PANSCK. is controlled by.

With such a configuration, the number of signal lines for operation panel control can be further reduced.

[Effects of the Invention] As is clear from the above, according to the present invention, in an electronic device having an operation panel composed of a plurality of light emitting elements and switch and switch elements, driving information of the light emitting elements,
In order to input the operation state of the switch elements, selection information for selecting each switch element is input in a time-sharing manner from the main control section of the device, and the driving of the light-emitting element and the switching element are performed in a time-sharing manner based on the input drive information or selection information. Since the configuration is equipped with a control means for inputting the operating status, the number of signal lines that control the operation panel can be significantly reduced, and there is no need to change the input/output means of the main body control system. It has excellent advantages such as reducing manufacturing costs by reducing the number of wires, easily ensuring safety, and easily ensuring compatibility even when multiple types of similar devices are manufactured.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of a printer adopting the present invention, FIG. 2 is a block diagram showing the structure of the operation panel shown in FIG. 1, and FIG. Figures 4 to 6 are block diagrams showing the control signal generation circuit on the printer engine side in Figures 2 to 3, and Figure 7 is a block diagram showing the structure of a different operation panel. FIG. 8 is a timing chart diagram for the structure of FIG. 7. 1... Printer 2... Carriage device 3.
...Panel 4...Printer engine 5...
・Controller 6...Power supply device 7...Connector 8...Host device 9...7 segment LE
D 10-17...LED 18-24...Switch 25...Shift register 26...Decoder 27...Connector 28...
・JK flip-flop 29.30.34...Latch 31...NAND gate 32...OR gate 51.52...Multiplexer 53...Parallel/serial shift register 58.5
9.71.72...Counter 61.62...Inverter 63...D flip-flop 80...Gate circuit

Claims (1)

[Scope of Claims] 1) In an electronic device having an operation panel composed of a plurality of light emitting elements and switch elements, each switch element is selected for inputting driving information of the light emitting element and operation state of the switch element. The apparatus is characterized by being provided with a control means for inputting selection information from the main control section of the device in a time-sharing manner, and driving the light-emitting element and inputting the operating state of the switch element in a time-sharing manner based on the input drive information or selection information. electronic equipment. 2) The electronic device according to claim 1, further comprising means for controlling a driving period of the light emitting element, and the amount of light emitted from the light emitting element is adjusted by the control means.