JPH0333074Y2 - - Google Patents
Info
- Publication number
- JPH0333074Y2 JPH0333074Y2 JP1985163691U JP16369185U JPH0333074Y2 JP H0333074 Y2 JPH0333074 Y2 JP H0333074Y2 JP 1985163691 U JP1985163691 U JP 1985163691U JP 16369185 U JP16369185 U JP 16369185U JP H0333074 Y2 JPH0333074 Y2 JP H0333074Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- chip
- substrate
- semiconductor package
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案はICやLSIなどのチツプを搭載するヒー
トシンク付半導体用パツケージに関するものであ
る。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor package with a heat sink that mounts a chip such as an IC or LSI.
近年、コンピユータ装置を始めとして種々の電
子機器に実装されるICは、素子の高集積化およ
び動作の高速化に伴い発生熱量、熱密度とも大幅
に増大している。ところで一般にICなどにとつ
ては熱は好ましいものではなく、信頼性の高い装
置を実現するためにはICの内部温度を規定温度
以下に抑える必要がある。このため、ICの温度
を抑制する手段や構造は極めて重要であり、大風
速流や冷気を装置内に供給するなどして対処した
り、ICチツプを搭載するパツケージ構造自身の
放熱特性の改善にも種々の工夫がなされている。
たとえば、パツケージの材質を樹脂材から熱伝導
率が高いアルミナ・ベリリア等のセラミツク材に
変更したり、パツケージを薄板化して熱流路を短
縮するなどにより放熱特性の向上を図ることが従
来より行われてきた。そして前述した改良によつ
ても放熱特性が不十分な場合は、第4図に示すよ
うに、くし歯状のヒートシンクを接着剤やろう材
によつてパツケージ本体に接合して能力を向上さ
せていた。
In recent years, the amount of heat generated and the heat density of ICs mounted in various electronic devices such as computer equipment have increased significantly due to higher integration and faster operation of the elements. By the way, heat is generally not desirable for ICs, and in order to realize highly reliable devices, it is necessary to keep the internal temperature of the IC below a specified temperature. For this reason, means and structures to suppress the temperature of ICs are extremely important, and measures such as supplying high wind speeds and cold air into the equipment, and improving the heat dissipation characteristics of the package structure itself that mounts the IC chips, are extremely important. Various efforts have also been made.
For example, conventional efforts have been made to improve heat dissipation characteristics by changing the material of the package from resin to ceramic materials such as alumina or beryllia, which have high thermal conductivity, or by making the package thinner and shortening the heat flow path. It's here. If the heat dissipation characteristics are still insufficient even after the above-mentioned improvements, the performance can be improved by bonding a comb-like heat sink to the package body using adhesive or brazing material, as shown in Figure 4. Ta.
第4図は従来のヒートシンク付半導体用パツケ
ージの一例を示す一部破断斜視図である。 FIG. 4 is a partially cutaway perspective view showing an example of a conventional semiconductor package with a heat sink.
同図において、基板1の一方の面にICチツプ
9が搭載され、かつ複数の入出力端子5が立設さ
れている。この基板1の他方の面にはくし歯形状
のヒートシンク2aがヒートシンク固着剤8によ
り接合されている。基板1のチツプ搭載面には、
さらにICチツプ9と基板1上に形成された接続
パツド6を接続するワイヤ11、および接続パツ
ド6と入出力端子5を結ぶパターン7が設けられ
電気的な接続がなされる。また基板1にICチツ
プ9を被覆するように固着されたキヤツプ12に
よりICチツプ9を機械的外力から保護するとと
もに外気より遮断している。ここで基板1には一
般にアルミナ板が使用され、ヒートシンク2aに
は線膨張係数が基板1と等しい材料が選択されて
いた。たとえば銅とタングステンの組成体あるい
は銅とモリブデンの組成体を使用し(実開昭59−
91742号公報)、基板1と接合一体化しても熱応力
の発生がなく、接合層の亀裂や剥離等が生じない
ようにするためである。 In the figure, an IC chip 9 is mounted on one surface of a substrate 1, and a plurality of input/output terminals 5 are provided upright. A comb-shaped heat sink 2 a is bonded to the other surface of the substrate 1 with a heat sink adhesive 8 . On the chip mounting surface of board 1,
Further, wires 11 for connecting the IC chip 9 and the connection pads 6 formed on the substrate 1, and patterns 7 for connecting the connection pads 6 and the input/output terminals 5 are provided for electrical connection. Further, a cap 12 fixed to the substrate 1 so as to cover the IC chip 9 protects the IC chip 9 from external mechanical forces and isolates it from the outside air. Here, an alumina plate is generally used for the substrate 1, and a material having the same coefficient of linear expansion as the substrate 1 is selected for the heat sink 2a. For example, using a composition of copper and tungsten or a composition of copper and molybdenum
91742), this is to prevent thermal stress from occurring even when the bonding layer is bonded and integrated with the substrate 1, and cracks and peeling of the bonding layer do not occur.
しかしながら、上述の従来使用している銅−タ
ングステンおよび銅−モリブデン組成体は、比重
がそれぞれ16および9であり非常に重いので取扱
いに難があり、主成分であるタングステンやモリ
ブデンは高価であるためパツケージの価格を引き
上げる要因になつていた。また、ICの高集積化
に伴うピン数の増大やチツプサイズの大型化によ
り、パツケージ外形が大きくなる傾向にあり、こ
のため基板1とヒートシンク2の接合面に残る気
泡が多くなる欠点があり、この気泡が熱伝導を妨
げる要因になつていた。
However, the conventionally used copper-tungsten and copper-molybdenum compositions mentioned above have a specific gravity of 16 and 9, respectively, and are very heavy and difficult to handle, and the main components, tungsten and molybdenum, are expensive. This was a factor in raising the price of package. In addition, as ICs become more highly integrated, the number of pins and chip sizes increase, which tends to increase the size of the package. Air bubbles were a factor that hindered heat conduction.
本考案のヒートシンク付き半導体用パツケージ
は、一方の面にチツプ搭載部、複数の入出力端子
および該入出力端子とチツプとを接続する接続パ
ツドが設けられ、他方の面にヒートシンクが接合
されたセラミツク板を備え、前記ヒートシンクは
アルミニウム材からなり、前記セラミツク板との
接合面に複数本の溝を有している。
The semiconductor package with a heat sink of the present invention is a ceramic package with a chip mounting part, a plurality of input/output terminals, and connection pads for connecting the input/output terminals and the chip on one side, and a heat sink bonded on the other side. The heat sink is made of an aluminum material and has a plurality of grooves on its joint surface with the ceramic plate.
次に、本考案について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第1図は本考案のヒートシンク付半導体用パツ
ケージの一実施例を示す一部破断斜視図、第2図
は第1図のA−A断面図、第3図は第1図におけ
るヒートシンクの三面図でa,b,cはそれぞれ
正面図、下面図、側面図である。 FIG. 1 is a partially cutaway perspective view showing an embodiment of a semiconductor package with a heat sink of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIG. 3 is a three-sided view of the heat sink in FIG. 1. A, b, and c are a front view, a bottom view, and a side view, respectively.
第1図、第2図において従来例と同じ構成要件
には第4図と同じ符号を付してある。同図におい
て、本実施例は複数の入出力端子5が立設された
平板状のアルミナ製の基板1にヒートシンク2が
接合されて構成される。基板1の一方の面である
下面のほぼ中央部には平滑な面上に形成された搭
載部4が設けられ、搭載部4に樹脂系接着剤等の
チツプ固着剤10によつてICチツプ9が固定さ
れる。ICチツプ9の電気的接続の構造およびキ
ヤツプ12の取付構造は従来例と同じである。 In FIGS. 1 and 2, the same components as in the conventional example are given the same reference numerals as in FIG. 4. In the figure, the present embodiment is constructed by bonding a heat sink 2 to a flat alumina substrate 1 on which a plurality of input/output terminals 5 are arranged upright. A mounting portion 4 formed on a smooth surface is provided approximately at the center of the lower surface of the substrate 1, and an IC chip 9 is attached to the mounting portion 4 using a chip fixing agent 10 such as a resin adhesive. is fixed. The electrical connection structure of the IC chip 9 and the mounting structure of the cap 12 are the same as those of the conventional example.
ここでヒートシンク2はアルミニウム材を用い
て底面が基板1とほぼ同一外形に作られ、基板1
との固着面ではない面には放熱フインが上方に突
出されたくし歯形状に形成される。本実施例のヒ
ートシンク2は、その底面で基板1と接合する面
に、線膨張率の差より生じる熱応力を分断すると
共に全体の伸びを吸収するために溝3を設けてあ
る。溝3は第3図に示すように、底面に縦・横方
向に複数本格子状に設け、基板1とヒートシンク
2とは全面では接合させない。このヒートシンク
2は高熱伝導率材の紛体を混入させたエポキシ系
樹脂接着剤等のヒートシンク固着材8によつて基
板1の搭載部4がある面とは反対の面に接合して
一体化される。固着作業時に接合層に残つた気泡
は溝3を通じて抜け易いので、従来の溝の無いヒ
ートシンクの場合より気泡の残存度は著しく小さ
くなる。固着層の気泡は熱伝導を阻害するもの
で、したがつて本実施例は従来例に比較して接合
層で熱伝導が妨げられることはなくなる。 Here, the heat sink 2 is made of aluminum and has a bottom surface that is approximately the same in shape as the substrate 1.
A radiation fin is formed in a comb-tooth shape projecting upward on the surface other than the surface to which it is fixed. The heat sink 2 of this embodiment is provided with grooves 3 on its bottom surface, which is joined to the substrate 1, in order to isolate thermal stress caused by the difference in coefficient of linear expansion and to absorb overall elongation. As shown in FIG. 3, a plurality of grooves 3 are provided in a lattice pattern in the vertical and horizontal directions on the bottom surface, and the substrate 1 and the heat sink 2 are not joined to each other on the entire surface. This heat sink 2 is bonded and integrated to the surface of the board 1 opposite to the surface on which the mounting portion 4 is located by a heat sink fixing material 8 such as an epoxy resin adhesive mixed with powder of a high thermal conductivity material. . Since air bubbles remaining in the bonding layer during the fixing work can easily escape through the grooves 3, the degree of air bubble remaining is significantly smaller than in the case of a conventional heat sink without grooves. Bubbles in the fixed layer obstruct heat conduction, and therefore, in this embodiment, compared to the conventional example, heat conduction is not hindered by the bonding layer.
本実施例の半導体用パツケージにおいては、
ICチツプ9において発生した熱はチツプ固着剤
10から基板1、ヒートシンク固着剤8を経てヒ
ートシンク2へと伝導され、ヒートシンク2から
周囲空気中へ放散されてICチツプ9の温度上昇
を抑制する。この時、基板1およびヒートシンク
2も温度が高くなりそれぞれの線膨張係数に応じ
て膨張する。基板1の材料であるアルミナの線膨
張係数が約7×10-6/℃に対し、ヒートシンク2
の材料であるアルミニウムは約24×10-6/℃であ
るので、伸びは約3.4倍も異なるが、溝3により
アルミニウムの伸びが吸収されるので全体の熱応
力は緩和される。したがつて接合層が剥離した
り、基板1に亀裂が生じることもなく、半導体用
パツケージの信頼性を向上させることができる。
しかもヒートシンク材であるアルミニウムの比重
は2.7であり、従来使用している銅−タングステ
ンあるいは銅−モリブデンと比較して1/6あるい
は1/3と非常に軽いので、半導体用パツケージを
軽量化できる。しかもアルミニウムは安価であ
り、比重が小さいため使用重量も少なくなること
と相まつて低価格のパツケージが提供できる。 In the semiconductor package of this example,
The heat generated in the IC chip 9 is conducted from the chip adhesive 10 to the heat sink 2 via the substrate 1 and the heat sink adhesive 8, and is dissipated from the heat sink 2 into the surrounding air to suppress the temperature rise of the IC chip 9. At this time, the temperature of the substrate 1 and the heat sink 2 also increases, and they expand according to their respective coefficients of linear expansion. The linear expansion coefficient of alumina, which is the material of the substrate 1, is approximately 7×10 -6 /℃, while the heat sink 2
Aluminum, which is the material of the material, has a temperature of about 24×10 -6 /°C, so the elongation is about 3.4 times different, but since the elongation of the aluminum is absorbed by the grooves 3, the overall thermal stress is alleviated. Therefore, the reliability of the semiconductor package can be improved without peeling of the bonding layer or cracking of the substrate 1.
Moreover, the specific gravity of aluminum, the heat sink material, is 2.7, which is 1/6 or 1/3 lighter than the conventionally used copper-tungsten or copper-molybdenum, making it possible to reduce the weight of semiconductor packages. Furthermore, aluminum is inexpensive and has a low specific gravity, which reduces the weight used, and together with this, a low-cost package can be provided.
なお、上記実施例においては樹脂系接着剤を用
いて基板1にヒートシンク2を接合したものにつ
いて説明したが、本考案はこれに限定されるもの
ではなく、たとえばろう材を用いたろう付けによ
り溶着してもよい。この場合ヒートシンク2の取
付面にろう付けを可能にする適合材料をあらかじ
め設けておけばよく、公知のメタライズ技術によ
り実現可能である。 In the above embodiment, the heat sink 2 is bonded to the substrate 1 using a resin adhesive, but the present invention is not limited thereto. You can. In this case, a compatible material that enables brazing may be provided in advance on the mounting surface of the heat sink 2, and this can be realized using a known metallization technique.
〔考案の効果〕
以上説明したように本考案は、アルミニウム材
からなるヒートシンクの複数本の溝を有する面を
セラミツク板に接合することにより、熱応力を小
さく抑制してセラミツク板の亀裂発生や接合層の
剥離を防ぐと共に、接合層に発生する気泡が少な
くなるので熱伝導の信頼性が向上し、かつ軽量で
安価なヒートシンク付半導体用パツケージが得ら
れる効果がある。[Effects of the invention] As explained above, the present invention suppresses thermal stress to a small level by bonding the surface of a heat sink made of aluminum with multiple grooves to a ceramic plate, thereby preventing cracks in the ceramic plate and bonding. This has the effect of preventing layer peeling and reducing the number of bubbles generated in the bonding layer, improving reliability of heat conduction and providing a lightweight and inexpensive semiconductor package with a heat sink.
第1図は本考案のヒートシンク付半導体用パツ
ケージの一実施例を示す一部破断斜視図、第2図
は第1図のA−A断面図、第3図は第1図におけ
るヒートシンクの三面図でa,b,cはそれぞれ
正面図、下面図、側面図、第4図は従来のヒート
シンク付半導体用パツケージの一例を示す一部破
断斜視図である。
1……基板、2,2a……ヒートシンク、3…
…溝、4……搭載部、5……入出力端子、6……
接続パツド、7……パターン、8……ヒートシン
ク固着剤、9……ICチツプ、10……チツプ固
着剤、11……ワイヤ、12……キヤツプ。
FIG. 1 is a partially cutaway perspective view showing an embodiment of a semiconductor package with a heat sink according to the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is a three-sided view of the heat sink in FIG. 1. Reference symbols a, b, and c are a front view, a bottom view, and a side view, respectively, and FIG. 4 is a partially cutaway perspective view showing an example of a conventional semiconductor package with a heat sink. 1... Board, 2, 2a... Heat sink, 3...
...Groove, 4...Mounting section, 5...Input/output terminal, 6...
Connection pad, 7... pattern, 8... heat sink adhesive, 9... IC chip, 10... chip adhesive, 11... wire, 12... cap.
Claims (1)
よび該入出力端子とチツプとを接続する接続パツ
ドが設けられ、他方の面にヒートシンクが接合さ
れたセラミツク板を備えるヒートシンク付半導体
用パツケージにおいて、前記ヒートシンクはアル
ミニウム材からなり、前記セラミツク板との接合
面に複数本の溝を有することを特徴とするヒート
シンク付半導体用パツケージ。 A semiconductor package with a heat sink, which is provided with a chip mounting part, a plurality of input/output terminals, and a connection pad for connecting the input/output terminals and the chip on one surface, and a ceramic plate with a heat sink bonded on the other surface, 1. A semiconductor package with a heat sink, wherein the heat sink is made of an aluminum material and has a plurality of grooves on its joint surface with the ceramic plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985163691U JPH0333074Y2 (en) | 1985-10-24 | 1985-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985163691U JPH0333074Y2 (en) | 1985-10-24 | 1985-10-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273551U JPS6273551U (en) | 1987-05-11 |
| JPH0333074Y2 true JPH0333074Y2 (en) | 1991-07-12 |
Family
ID=31092127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985163691U Expired JPH0333074Y2 (en) | 1985-10-24 | 1985-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0333074Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6308780B2 (en) * | 2013-12-27 | 2018-04-11 | 三菱電機株式会社 | Power module |
-
1985
- 1985-10-24 JP JP1985163691U patent/JPH0333074Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6273551U (en) | 1987-05-11 |
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