JPH033389B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a field effect integrated semiconductor device. More specifically, the present invention provides self-aligned metal-to-silicon contacts and submicron contact-to-contact contacts where the insulator between the contacts is a pattern of dielectric material having submicron thickness dimensions. A self-aligned metal process for achieving polycrystalline silicon gate electrodes with metal-to-metal spacing.

For semiconductor integrated circuits, the integration density has increased considerably over the past decade. However, new applications such as microprocessors and microcomputers are creating increasing demands for higher integration, faster switching speeds, and smaller devices. Field effect transistor technology is dominant in main memory and low performance logic arrays due to its higher circuit density and simpler process compared to bipolar technology.

A very active area in semiconductor manufacturing technology has been the development and application of fine lines and line separation in lithographic techniques. In lithographic processes, until very recently, light has been used almost exclusively to expose photosensitive films. However, it is extremely difficult to further advance the technology to obtain finer line widths and line separations due to limitations in optical resolution. In future technology to obtain reduction in line width and line spacing, electron beam and X-ray exposure processes are very important and applicable techniques. For more information on lithography problems and their possible solutions, read DL Critchlow’s “High Speed”
MOS FET Circuits Using Advanced
Lithography”, the Computer, Vol.9, No.2,
February 1976, pp. 31-37. In that publication, the cost and complexity of x-ray and electron beam lithography equipment is discussed.

1 by extending standard photolithography techniques and avoiding the need for expensive and complex techniques such as electron beam or X-ray lithography.
Alternative efforts have been made to obtain fine line widths and line spacings of micrometers or more. One such technique is the HBPogge paper,
IBM Technical Disclosure Bulletin;
November 1976, Vol.No.6 “Narrow Line
This method uses porous silicon and oxidizes the porous silicon. Still other techniques are described by SAAbbas et al.
IBM Technical Disclosure Bulletin Vol.20,
No. 4, September 1977, pp. 1376-1378. This TDB describes the use of a polycrystalline silicon masking layer which is formed as a mask by first using an intermediate mask of oxidized blocking material such as silicon nitride in the formation of polycrystalline silicon. Linear dimensions of approximately 2 micrometers or less can be obtained with this technique. TNJackson et al. also published a paper “A Novel Sub-micron Fabrication
Technique” (March 1980, Semiconductor
International pp77-83). This method for making submicron linewidths and devices does not require electron beam lithography and
Uses selective edge plating technology.
UKP2003660 discloses a method for depositing areas of metal, for example by providing metal on a substrate, and forming thin metal strips by using unidirectional plasma etching techniques. No. 4,083,098 discloses a method for forming a plurality of closely spaced conductive layers (separated by air space) on an insulated substrate. No ohmic connection to the silicon body beneath the insulator supporting the conductive layer is disclosed. Although the techniques described above represent a method for forming thin lines on a substrate, they do not represent a complete solution for effective use in semiconductor device manufacturing. That is, there is no clear indication of how these techniques can be used to contact actual device elements into a semiconductor substrate in an accurate and effective manner. Furthermore, the first
There are problems with the flatness of the metallurgy at the level and the moderate conductivity of the metallurgy at that level.

Other techniques, such as those disclosed in USP 4,234,362, include techniques for forming regions of narrow dimensions, e.g. submicron dimensions, on a semiconductor body, including formation in silicon body regions having substantially horizontal surfaces and substantially vertical surfaces. is disclosed. Layers of very narrow dimensions are formed on both substantially horizontal and substantially vertical surfaces. Reactive ion etching is used on the layers to remove the substantially vertical layers, leaving the vertical layers substantially intact. Vertical layer dimensions are adjusted depending on the original thickness of the layers used. In this art, emphasis is placed on techniques for using this narrow dimension area in semiconductor device control processes for various types of integrated circuit structures, such as field effect devices.

A major problem in very high density integrated circuits is the electrical contacts for the various elements and devices in the semiconductor integrated circuit. As device density increases, problems with metallurgy conductivity at various levels become involved. Recently, the direction of solution to these problems is USP3750268 and
There is a trend towards using highly doped polycrystalline silicon as the conductive layer as shown in US Pat. No. 3,984,822. However, as device density increases, problems still exist regarding isolation between devices, particularly conductivity in first level metallurgy contacting semiconductor devices, as well as alignment of multiple levels of metallurgy to device elements in semiconductor integrated circuits. .

A common method for forming dual polycrystalline silicon multilayer structures uses silicon dioxide as an insulator between the layers. The thickness of the silicon dioxide layer between the two polycrystalline layers is usually directly related to the thickness of the silicon gate oxide from which the FET type device is formed. Conventional thermal oxidation techniques are used to form the silicon dioxide layer.

An object of the present invention is to narrow the width of an insulator adjacent to both sides of a silicon gate electrode and a metal electrode for source/drain, and utilize the vertical sides of the insulator to place a metal electrode in a source/drain region. An object of the present invention is to provide a method for manufacturing an integrated circuit that can be self-aligned.

FET having a pattern of dielectric regions of narrow dimensions on a body of a single crystal semiconductor, preferably silicon
A method for forming an integrated circuit includes a process of providing a silicon body and forming a first insulating layer on a major surface of the body. A highly doped polycrystalline silicon layer and a silicon nitride layer are then formed over the first insulating layer. Openings are made in the silicon nitride and polycrystalline layers by using directional reactive ion etching that yields structures with substantially horizontal and substantially vertical surfaces. The openings are formed in regions designated to be the gate regions of FETs in the integrated circuit. A second insulating layer is then deposited on both the generally horizontal surface and the generally vertical surface. The thickness of the second insulating layer is that desired to ultimately form dielectric regions of narrow dimensions on the semiconductor (preferably silicon). The structure is subjected to a vertically oriented reactive ion etching atmosphere to substantially remove the second insulating layer from the horizontal surfaces. This directional etching does not significantly affect the insulating layer in the vertical regions of polycrystalline silicon. The semiconductor body is subjected to a heating cycle to suitably drive down the dopant from the polycrystalline silicon layer into the semiconductor body in intimate contact with the layer. A gate dielectric layer is formed.
A polycrystalline second doped layer is formed and a plastic layer, such as polyimide or photoresist, is coated thereon. The second polycrystalline silicon layer and the plastic layer are etched at the same etch rate using reactive ion etching until the silicon nitride layer is exposed. A pattern is formed in the remaining second polycrystalline layer;
A silicon dioxide layer is thermally grown on the surface of the polycrystalline layer. The exposed silicon nitride and first polycrystalline silicon regions are then removed by etching to leave free-standing thin-sized dielectric regions at the surface of the silicon body. By using less stringent masking techniques, the portion of the silicon dioxide layer overlying the second polycrystalline silicon and the portion of the narrow dielectric region away from the FET region are removed. One or more dielectric layers of a wide variety of materials are removed from the source/drain using a lift-off mask.
It is deposited on top of the narrow dimension area as well as the silicon body to form a contact to the PN area. If a conductive layer is formed on bare silicon, ohmic contacts can be made thereto. A plastic material, such as polyimide or photoresist, is deposited over this conductive layer to flatten its surface. The structure is then placed in a reactive ion etching atmosphere to uniformly etch the conductive layer along with the plastic layer up to the top of the narrow dimension areas. The remaining plastic material is then removed to form a generally planar conductive layer with narrow dimensions of dielectric insulation separating portions of the conductive layer from other portions of the conductive layer and polysilicon gate electrode. .

The method can be used to form a variety of FET products. The structure of this is an appropriate PN
The junctions, gate dielectric and electrode structures, PN contact regions, and openings to the semiconductor body in which these devices are formed are formed by appropriate modifications of the above-described methods. Logic and memory FET integrated circuits can be formed according to these methods to give favorable results of high densities with metallurgy layers of suitable conductivity, good planarity, and associated yield and reliability. can.

The method can be applied to form short channel FET integrated circuits. The structure includes a semiconductor body having a pattern of dielectric regions of narrow dimensions on a major surface of the silicon body. A gate dielectric layer is disposed on the major surface between portions of the narrow dimension region. A PN junction source/drain region is located directly beneath a portion of the narrow dimension region and is associated with a short channel beneath the gate dielectric layer. A polycrystalline silicon gate electrode is disposed on the surface of the gate dielectric layer between certain narrow dimension regions. Metallic electrical contacts are formed to the ends of the PN junction regions and fill the spaces between the remaining narrow dimension regions. These contacts are self-aligned to the narrow dimension region and are approximately in the same plane as the top of the narrow dimension region.

Referring to FIGS. 1-11, a first embodiment is shown using a self-aligned metal process to form a FET integrated circuit. The process is shown to form an N-channel MOS FET integrated circuit. However, it is of course possible to form a P-channel FET by simply reversing the polarity of the various elements of the transistor and their associated regions. FIG. 1 is an enlarged view of a small portion of a silicon body used to form a very high density FET integrated circuit structure. A near-intrinsic P-type substrate 2 with a resistivity of 20 to 100 ohm-cm is the preferred substrate for this method. Instead, 10 to
A p-type substrate made of single crystal silicon with a resistivity of 20 ohm-cm can be used as the basic structure for this method. A P+ substrate with lightly doped P epitaxy can also be used.

The first series of method steps includes the process of forming insulating means for insulating certain areas of the single crystal silicon from other areas of the single crystal silicon in the substrate 2. The insulation is preferably patterned with partial dielectric insulation 10 using materials such as silicon dioxide, glass, etc. to define the surface area of the single crystal silicon that will ultimately form the FET device. Below the dielectric insulation there is a P ion implantation region 8 to prevent surface leakage at the interface between the substrate and the dielectric insulation. Various conventional techniques exist for forming this type of dielectric isolation region.
Preference is given to using processes such as those shown in UKP1323850, UPS3648129 and UPS4104086. In these prior art processes for forming partial dielectric isolation region 10 are shown in detail. However, the process merely refers to forming a silicon dioxide layer 4 on top of the silicon body. On top of that a layer of silicon nitride 6
is formed. Layers 4 and 6 are removed by conventional lithography in areas designated to have dielectric isolation areas. P region 8 is formed by ion implantation using boron as an impurity to form the structure of FIG. The structure is placed in an oxidizing atmosphere until silicon dioxide dielectric isolation region 10 is formed. Layers 4 and 6 are removed by etching to obtain the structure of FIG. An insulating layer 11 of silicon dioxide and an insulating layer 12 of silicon nitride are formed on the surface of the body. Conventional lithography and etching techniques are used to remove layers 11 and 12 in the active device areas as shown in FIG.

The first insulating layers 11, 12 are shown to be formed from silicon dioxide and silicon nitride. However, the first insulating layers 11, 12 can be any of silicon dioxide, silicon nitride, aluminum trioxide, or a combination thereof. The layer can be grown thermally, for example, in an oxygen or oxygen-water vapor atmosphere at a temperature of about 970 DEG C. to form a thermal silicon dioxide layer. A second method for forming silicon dioxide involves chemical vapor deposition using SiH ₄ and O ₂ at about 450° C. or SiH ₂ Cl ₂ and N ₂ O at about 800° C. under atmospheric or low pressure conditions. There is a process. Typically, silicon nitride deposits are formed by chemical vapor deposition using the following process conditions. That is, under conditions of atmospheric pressure or low pressure as shown in USP 4089992, approximately
Carrier of SiH ₄ , NH ₃ and N ₂ at a temperature of 800℃
Gas is used. The insulating layer 12 has a thickness of approximately
It is 1500〓.

A polycrystalline silicon overlayer 18 is deposited over the entire wafer, for example by using silane in a hydrogen atmosphere at a temperature in the range of about 500 to 1000°C. The operable thickness of polycrystalline silicon is between about 7,000 and 12,000 Å, with 10,000 Å being preferred. Generally, it is preferred that the first polycrystalline silicon layer is approximately equal to the thickness of the metal. If it is too high, that part protrudes too much from the metal,
A first level of non-flatness occurs. If the area is too low, planarizing the metal and cutting the metal becomes more difficult. Doping the polycrystalline silicon layer with N ⁺ type impurities can be done by doping the N+ impurity during the deposition of the polycrystalline silicon layer, or by ion-implanting the N+ impurity following the deposition of the polycrystalline silicon layer. formed by Phosphorus is a suitable impurity for this doping. The polycrystalline silicon layer is in contact with the silicon body in areas without the first insulating layers 11, 12. A silicon nitride layer 20, for example about 500 Å thick, is chemical vapor deposited by decomposing SiH ₄ and N ₂ at 800° C. to obtain the structure of FIG. Other suitable insulating layers or combinations of insulating layers may be used in place of the silicon nitride layer.

Standard photolithography and etching techniques can be used to form openings in this silicon nitride layer 20 over areas designated to be the gate areas of the integrated circuit. Using the silicon nitride mask, the structure is placed in a reactive ion or plasma etching atmosphere for polycrystalline silicon with conditions as described below.

The above conditions are, for example, CF ₄ /argon, Cl ₂ /argon or CCl ₄ /argon, SF ₆ or
SF ₆ +Cl ₂ , RF parallel plate structure, pressure of about 10 microns, power density of 0.16 watts/cm ² and 10
The flow rate is cc/min.

The reactive ion etching process is completed when it reaches the monocrystalline silicon body 2. The resulting structure has horizontal and vertical surfaces.

A conformal layer 26 is deposited on both its generally horizontal and generally vertical surfaces (not shown). The conformable layer 26 is typically formed by chemical vapor deposition. The conformal layer must be an electrical insulator as formed or capable of being converted into an insulator. One of several insulators may be used as layer 26, such as silicon dioxide, silicon nitride, aluminum trioxide, and combinations of these materials with polycrystalline silicon. The shape conforming layer 26 used in this embodiment has approximately 3,000 to 10,000 layers.
silicon dioxide having a thickness of approximately 6000 Å (preferably about 6000 Å).

The structure is placed in a reactive ion etching atmosphere suitable for the material of conformal layer 26. For example, in etching silicon dioxide, conditions are preferred that result in an etch ratio of about 10 to 1 silicon dioxide to silicon. Overetching may be necessary to ensure that all silicon dioxide is removed from the horizontal surfaces, and/or an etch stop indicator may be used. A reactive ion etching process substantially removes the horizontal portions of layer 26 and forms a pattern of vertical regions 26 of narrow dimensions on the silicon body, as shown in FIG. Source/drain N+ regions 19 are formed by outdiffusion from first polycrystalline silicon layer 18.
This is accomplished by heating the substrate to about 1000° C. in a typical heating cycle of about 30 minutes.

Referring to FIG. 6, P regions 24 are formed in the exposed major surface of the silicon body between regions 26 of narrow dimensions by low energy ion implantation of boron at appropriate doses. P region 24 is a channel for FET devices formed in the active region. The result of this process is the sixth
As shown in the figure.

The structure of FIG. 6 is then exposed to a thermal oxidizing atmosphere to form a silicon dioxide gate dielectric 28. Gate dielectric thickness is approximately 200 to 500 mm
Å (preferably about 450 Å).

A second layer of N+ doped polycrystalline silicon 30
A layer is formed on the entire major surface of the structure as shown in FIG. 7 in the same manner as described above. N+ doping can be done as deposited or by phosphorus ion implantation after polycrystalline silicon deposition. A photoresist or polyimide layer 31 is deposited over the N+ polycrystalline silicon layer 30. The structure is made of a selected photoresist material 3
1 and N+ polycrystalline silicon 30 is placed in a reactive ion etching atmosphere exhibiting equivalent etching rates between N1 and N+ polycrystalline silicon 30. Overall ion etching is the 8th
As shown in the figure, the polycrystalline silicon 30 remains only in the designated gate electrode region until it reaches the silicon nitride layer 20. After patterning the polysilicon 30 in a pattern, a silicon dioxide layer 32 approximately 400 Å thick is grown on the surface of the second polysilicon gate electrode region 30 to yield the structure of FIG. . Silicon nitride layer 20 is removed with hot phosphoric acid H ₃ PO ₄ . The structure is placed in a reactive ion etching atmosphere for polysilicon to remove the remaining first polysilicon layer 18 and form the structure of FIG. By using a non-rigid mask, portions of silicon dioxide 32 and 26 are
removed from the FET region.

Using a suitable lift-off mask, narrow dimension dielectric region 26, gate electrode region 3
0, 32, and a metal layer 34 in the area between them.
is attached. Thus, in the areas between dielectric regions of narrow dimensions with contact openings to the PN junction elements, such as source/drain regions 19 in the silicon body, metal is ohmicly contacted to those regions. The structure is not completely planar because the metal layer forms a hilly surface over the narrow dimension dielectric region 26 and gate electrode regions 30,32. A preferred metal layer is an aluminum-copper layer deposited using vapor deposition or sputtering. A number of metals that can be used as blanket metals include aluminum, chromium/aluminum-copper. Unplanar blanket metallization structures are planarized by blanket depositing plastic material 35 over the metal layer. The plastic material may typically be a photoresist or a polyimide material. plastic material is 100
The wafer is spun over the surface of the wafer in a conventional manner, such as at 4500 rpm for 2 seconds. The polyimide is slowly cured at 80°C for 15 minutes and then at 300°C for 20 minutes. The resulting structure is shown in FIG. The planarized structure is placed in a reactive ion etching atmosphere. CCl ₄ /Ar atmosphere, 100 micron Hg,
Etchback is typically performed at 0.25 watts/cm ² . Reactive ion etching uniformly etches the plastic and metal layers down to the top of dielectric region 26 of narrow dimensions. The remaining plastic material is removed, for example, by oxygen ashing or other suitable process. The result of the process is the generally flat structure shown in FIG. The source/drain metal contact is shown at 34 and the gate electrode is shown at 30.

FIG. 12 shows a cross-sectional view of the structure of FIG. 11. FIG. 11 is a sectional view taken along line 11-11 in FIG. 12. The width of the metal parts and the spacing between the metal parts determine the device dimensions in the prior art, where the device dimensions are primarily determined by the lithography of the silicon process. A more flat first level metal section is obtained. Higher densities are obtained for the same lithographic basic scheme. In addition, 100% diffusion and gate area coverage can be achieved. In FIG. 12, the metal pattern is shown contacting the N+ polysilicon pattern 30 at its ends. The metal contact is made in areas where the silicon dioxide layer 32 covering the polysilicon pattern 30 was initially removed using a loose mask. Alternatively, contact can be made to polycrystalline silicon pattern 30 by a higher level metallization pattern through contact openings in silicon dioxide 32.

A second embodiment is shown in FIGS. 13 to 20. 1 to 12 illustrate a process for forming a dielectric isolation 10 buried on the surface region of an intrinsic silicon substrate 2 to insulate a single crystal silicon region designated as a region for a FET device. The method is carried out according to the procedures presented in connection with the examples presented in . Figure 1 or 1
The same numbers are used for structures as in the embodiment shown in FIG.

A first insulating layer 12 of silicon nitride is deposited by chemical vapor deposition as described above. The layer thickness is approximately 1500 Å. Conventional lithography and etching are used to pattern silicon nitride layer 12 to expose all active device areas, as shown in FIG. A silicon dioxide mask layer 44 is formed on the surface of the active semiconductor region by chemical vapor deposition of silicon dioxide, followed by standard lithographic and Use etching. The preferred etch is a reactive ion etch, which produces substantially vertical sidewalls of mask 44. The exposed silicon body 2 acts as an endpoint detector.

Please refer to FIG. Reactive ion etching continues using mask 44 to etch the silicon body to a depth of approximately 0.8 micrometers. Using silicon dioxide mask 44 and oxide insulating region 10 as a mask for the ion implantation, oxygen ions at a suitable concentration and dose are implanted into the exposed silicon surface. The body is annealed at about 800°C to 1000°C to form silicon dioxide layer 46. Note that the ion implantation process is directional such that only the horizontal surfaces of the exposed silicon body 2 are affected by the ion implantation process. The vertical regions are unaffected by the ion implantation process, leaving silicon regions as shown in FIG.

According to the process described above, N is deposited by chemical vapor deposition.
+Deposit doped polycrystalline silicon layer 18.
The process of depositing in a doped state (in
Instead of an in situ doping process, the polysilicon is N+ doped by phosphorus ion implantation subsequent to polysilicon deposition. A coating of photoresist or other suitable material (not shown) is applied to obtain a flat top surface. This coating should have an etch rate that ensures an etch rate in reactive ion etching that is equal to or slightly less than that of the polycrystalline silicon layer. Reactive ion etching
The process generally etches the coating and polycrystalline silicon protrusions, resulting in flat polycrystalline silicon patterns 18 separated by silicon dioxide masks 44 as shown in FIG. The remaining photoresist can be removed by oxidative ashes. Silicon nitride 20 is obtained on polycrystalline silicon layer 18 by ion implantation of a suitable dose of nitrogen at low energy and annealing at about 1000°C to 1200°C. N+ source/drain regions 19 are formed through vertically exposed regions of silicon body 2 during the annealing cycle described above.
+ It is formed by out-diffusion from the polycrystalline silicon layer 18.

Mask 44 is removed using a suitable immersion chemical etching process. A conformal layer of silicon dioxide 22 approximately 1 micrometer thick is deposited over the structure using standard chemical vapor deposition as described above. The structure is then placed in a directional reactive ion etching atmosphere. This etching atmosphere acts to remove the horizontal layer of the first conformal insulating silicon dioxide cladding 22 and to provide narrow openings to the exposed surface of the single crystal silicon surface area of the body 2 between the vertical surfaces of the insulating cladding. do. Ion implantation at a suitable dose at low energy is used to obtain a short channel region 24 of P type in the exposed silicon surface, as shown in FIG.

Silicon dioxide mask 22 is removed by standard immersion chemical etching to obtain the structure of FIG. A second conformal covering 26 is applied to both the substantially vertical and substantially horizontal surfaces. The thickness of the coating is on the order of 0.5 microns. To obtain the structure of FIG. 18, the horizontal layers are removed and directional reactive ion etching is used to provide a pattern of narrow dielectric regions 26 on the silicon body.

The exposed surface of the monocrystalline silicon body 2 is thermally oxidized between certain areas of narrow dimensions thereof to form gate dielectric regions 28 for the integrated circuit. Preferably, the gate dielectric oxide is about 400 Å thick. A second layer of N+ doped polycrystalline silicon 30 is deposited by chemical vapor deposition as described above. As previously mentioned, N+ doping can be applied to the polycrystalline silicon layer during formation or by ion implantation of phosphorus into the layer after formation. The structure is planarized using a photoresist or similar material and a reactive ion etching procedure as previously described in connection with planarization of the first layer of polycrystalline silicon 18. This procedure results in a flat structure with a polycrystalline silicon layer 30 formed as a gate electrode, as shown in FIG. After forming the pattern in polycrystalline silicon 30, the surface of layer 30 is exposed to a thermal oxidizing atmosphere to grow a silicon dioxide layer 32 of approximately 400 Å as shown in FIG.

As shown in Figure 20, normal wet etching
The silicon nitride layer 20 is removed by a process. The remaining first polycrystalline silicon layer 18 is then removed by a reactive ion etching process. A loose mask is used to remove silicon dioxide 32 and a portion of layer 26 in areas away from the FET areas. The process is carried out sequentially to form an aluminum/copper layer 34 of approximately 1.6 microns. Removal of the aluminum/copper layer 34 in undesired areas may be accomplished using a lift-off mask technique as shown in USP 4004044. Second
To obtain the final structure shown in FIG. 0, a planarization process as described in connection with the first embodiment shown in FIGS. 1-12 is carried out.
A structure shown in the same plan view as shown in FIG. 12 is obtained by the process of the second embodiment which yields the vertical structure of FIG.

The length of the P short channel region 24 is, for example, even if a basic photolithography method of 2.5 microns is used.
It is easy to make it to any desired submicron size of 0.5 micron. Unlike normal DMOS,
It is important to note that the FET of FIG. 20 is bilateral, or symmetrical, in that the source and drain functions can be easily interchanged during circuit operation. The overlap capacitance of the gate electrode on the source/drain is approximately zero. Source/drain-to-substrate parasitic capacitance has been reduced by the introduction of a dielectric layer 46 of silicon dioxide. The only area where this small capacitance occurs is the lateral N+ diffusion 19 of approximately 0.6 microns.

[Brief explanation of drawings]

1 to 11 are diagrams illustrating a first process for forming an integrated circuit device of the present invention, and FIG. 12 is a plan view of a structure formed by the process shown in FIGS. 1 to 11. Figures 13 to 20
The figure is a diagram illustrating a second process for forming an integrated circuit device of the present invention. 2...Silicon body, 4...Silicon dioxide layer, 6...Silicon nitride layer, 8...Ion implantation region, 10...Dielectric insulating part, 11...Silicon dioxide layer, 12...Silicon nitride layer, 18 ... Polycrystalline silicon layer, 19 ... Source/drain N+ region, 20 ... Silicon nitride layer, 24 ... Ion implantation region, 26 ... Shape matching layer, 30 ... Silicon gate electrode region, 31 ... Photo resist,
32...Silicon dioxide layer, 34...Metal layer, 3
5...Plastic material.

Claims (1)

[Claims] 1. Source and drain regions and a gate insulating layer on the surface of a silicon semiconductor substrate, and a gate electrode layer of polycrystalline silicon on the gate insulating layer,
A method of manufacturing a field effect transistor integrated circuit having an electrode metal layer for the source and drain regions self-aligned with the gate electrode layer adjacent an outer surface of a narrow width insulator, comprising: A polycrystalline silicon layer doped with impurities of a conductivity type having vertical inner wall openings is provided on a semiconductor substrate of an opposite conductivity type, and the impurities are diffused into the semiconductor substrate to form source and drain regions. and exposing the semiconductor substrate to an insulating substance deposition atmosphere to deposit an insulating layer on the polycrystalline silicon surface including the substantially vertical inner wall surface of the opening and the exposed surface of the semiconductor substrate, selectively vertically depositing the semiconductor substrate. exposing the substrate to a directional reactive etching atmosphere for etching until the surface of the semiconductor substrate is exposed to the opening, and etching the substrate including the peripheral wall of the insulator with a narrow width remaining on the inner wall of the opening. By sequentially forming a gate insulating layer and a gate electrode polycrystalline silicon layer on the semiconductor substrate using the crystalline silicon layer as a mask, and selectively removing the masking polycrystalline silicon layer by exposing it to an etching atmosphere, A polycrystalline silicon layer for a gate electrode having a peripheral wall of the insulator on an approximately vertical outer surface remains, and a metal layer is formed on the surface of the semiconductor substrate using the polycrystalline silicon layer for a gate electrode surrounded by the peripheral wall of the insulator as a mask. A method of manufacturing an integrated circuit as described above, comprising depositing and forming self-aligned metal layers for source and drain electrodes.