JPH0334372U - - Google Patents
Info
- Publication number
- JPH0334372U JPH0334372U JP9552789U JP9552789U JPH0334372U JP H0334372 U JPH0334372 U JP H0334372U JP 9552789 U JP9552789 U JP 9552789U JP 9552789 U JP9552789 U JP 9552789U JP H0334372 U JPH0334372 U JP H0334372U
- Authority
- JP
- Japan
- Prior art keywords
- level
- voltage
- output signal
- circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
- Picture Signal Circuits (AREA)
Description
第１図はこの考案の一実施例を示す回路図、第
２図及び第３図はこの考案の回路の特性を説明す
るために示した特性図、第４図は従来のコントラ
スト改善回路を示す図、第５図はクランプ回路の
動作を説明するために示した波形図、第６図及び
第７図は従来のコントラスト改善回路の特性を説
明するために示した特性図である。
２１……コンデンサ、２２……スイツチ、２３
，２８，２９……電圧源、２４，２５，２６，２
７……抵抗、３０……バツフア増幅器。
Fig. 1 is a circuit diagram showing an embodiment of this invention, Figs. 2 and 3 are characteristic diagrams shown to explain the characteristics of the circuit of this invention, and Fig. 4 shows a conventional contrast improvement circuit. 5 are waveform diagrams shown to explain the operation of the clamp circuit, and FIGS. 6 and 7 are characteristic diagrams shown to explain the characteristics of the conventional contrast improvement circuit. 21...Capacitor, 22...Switch, 23
, 28, 29... Voltage source, 24, 25, 26, 2
7...Resistor, 30...Buffer amplifier.
Claims (1)
フア増幅器に導く経路に設けられ、前記出力信号
のレベルが第１のレベルより低い場合にオンして
前記出力信号を第１の分圧回路により分圧して前
記バツフア増幅器に導き、前記出力信号が前記第
１のレベルより高く第２のレベルより低い場合は
そのまま前記バツフア増幅器に導き、前記出力信
号が前記第２のレベルより高い場合は第２の分圧
回路により分圧して前記バツフア増幅器に導き、
前記第１の分圧回路が動作するときの入力出力特
性と前記第２の分圧回路が動作するときの入力出
力特性の傾斜を、前記第１第２の分圧回路がオフ
しているときの入力出力特性の傾斜よりも緩やか
に設定した入力レベル可変回路を備えたことを特
徴とするコントラスト改善回路。 A first voltage dividing circuit is provided in a path leading the output signal clamped by the clamp circuit to the buffer amplifier, and is turned on when the level of the output signal is lower than a first level, dividing the output signal by the first voltage dividing circuit. If the output signal is higher than the first level and lower than the second level, it is routed directly to the buffer amplifier, and if the output signal is higher than the second level, it is routed directly to the buffer amplifier, and if the output signal is higher than the second level, it is routed to a second voltage divider circuit. divides the voltage by and leads it to the buffer amplifier,
The slope of the input-output characteristic when the first voltage-dividing circuit operates and the input-output characteristic when the second voltage-dividing circuit operates when the first and second voltage-dividing circuit is off. A contrast improvement circuit characterized by comprising an input level variable circuit whose input level is set more gently than the slope of the input/output characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9552789U JPH0334372U (en) | 1989-08-16 | 1989-08-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9552789U JPH0334372U (en) | 1989-08-16 | 1989-08-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0334372U true JPH0334372U (en) | 1991-04-04 |
Family
ID=31644785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9552789U Pending JPH0334372U (en) | 1989-08-16 | 1989-08-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334372U (en) |
-
1989
- 1989-08-16 JP JP9552789U patent/JPH0334372U/ja active Pending
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