JPH0334571A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the rise of contact resistance so as to obtain low contact resistance by making it have a trench in the inward direction of a diffusion layer right below an opening, and forming a diffusion layer region above the depth of the trench at the periphery of the trench. CONSTITUTION:Diffusion layers 11a, wherein N-type impurity is diffused, exist as source and drain regions at one part of a P-type silicon semiconductor substrate 10, and one part of each diffusion layer 11a has a part 11b, which is diffused deep in the inward direction of an Si substrate 10. One part of the diffusion layer 11a is provided with a contact part 12a bored through an insulating film 12, and at the contact part 12a, the diffusion layer 11a is cut 0.2mum in depth with the opening area. Metallic electrodes 13 are in contact with the diffusion regions 11a in source and drain regions through respective contact parts 12a. That is, by providing a trench in the inward direction of the diffusion layer in contact with the electrode, the effective contact area is expanded, whereby the rise of contact resistance can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device such as a very large scale integrated circuit (VLSI) that connects a semiconductor region and an electrode, and a method for manufacturing the same.

Conventional Technology Conventional Figure 5 shows a cross-sectional structure of a part of a MOS transistor when a metal electrode is formed in a diffusion layer that is a part of a transistor region in a VLSI. There is a diffusion layer 11 in which N-type impurities are diffused as source and drain regions in a part of the substrate 10, and there is an insulating film 12 in which a contact part 12a is provided by opening a part of this diffusion layer 11. The electrode 13 that contacts the diffusion region 11 of the source and drain regions through the portion 12a is also the gate electrode 14 in the figure. Contact resistance (hereinafter referred to as contact resistance) exists in the contact portion between the silicon (hereinafter referred to as Si) semiconductor of the diffusion layer and the metal as described above. This contact resistance is influenced by the area of the contact portion 12a. However, with this configuration, the problem that the invention aims to solve is that the product of contact resistance and contact size has a constant relationship when the contact size is 2 μm. are also affected by high integration.
When contact size is reduced, contact resistance increases. Let this contact resistance be Rc ohm (Ω〉)
Assuming that the contact size is S square cm (Cm'), when the contact size is 1 μm2 or more, the following relationship holds true as a rule of thumb: RCXS (Ω・0m2) = constant As is clear from this relationship, the contact resistance increases with the contact size. be strongly influenced. Furthermore, when the contact size becomes 1 μm2 or less, RCXS tends to increase. An increase in contact resistance causes a serious problem in, for example, a MOS transistor, in which the speed of the upper transistor is reduced.

The present invention has been made in view of the above-mentioned problems, and aims to solve the problems by preventing a sudden increase in contact resistance even when the contact size is miniaturized and providing a semiconductor device having low contact resistance. Means for Solving the Problems The present invention solves the above-mentioned problems.A diffusion layer formed in a part of a semiconductor substrate, an opening formed in a part of the diffusion layer, and a diffusion layer formed in a part of the semiconductor substrate through the opening. The semiconductor device has a groove inward of the diffusion layer directly under the opening, and a diffusion layer region having a depth equal to or greater than the depth of the groove at the outer periphery of the groove. .

Effect of the present invention With the above-described structure, the effective contact area can be increased by providing a groove in the inner direction of the diffusion layer in contact with the electrode (de), and an increase in contact resistance can be prevented. By having a diffusion layer region with a depth equal to or greater than the depth of the groove, it is possible to suppress an increase in junction leakage between the semiconductor substrate and the diffusion layer. 1 shows a cross-sectional structural diagram of a semiconductor device according to the present invention. In the figure, a P-type silicon semiconductor substrate 10
There is a diffusion layer 11a in which N-type impurities are diffused as a source and drain region in a part of the Si substrate 10, and a part of this diffusion layer 11a is a part 11b which is diffused deep inside the Si substrate 10.
have.

In a part of the diffusion layer 11a, a contact portion 12a is provided by opening the insulating film 12, and the contact portion 12a is formed by cutting the diffusion layer 11a to a depth of 0.2 μm by the opening area. Although it is in contact with the diffusion region 11a of the source and drain regions through the contact portion 12a, and in the same figure, 14 is the gate electrode. The contact resistance was determined by the Kelvin bridge method. (a) shows the configuration according to the present invention, and (b) shows the conventional configuration. The contact resistance values determined by this measurement method are shown in FIG. Even though the contact resistance value according to the present invention is a very small value compared to the conventional one, this resistance value it xμ
d with a contact of m opening (contact area x2μm2)
The effective surface area when cut to a depth of is (x”+4dx)
Compared to the conventional contact resistance, it is approximately x" / (x" + 4 d x) times smaller. This means that an increase in contact resistance can be prevented even when a fine contact is formed.

(Embodiment 2) FIG. 4 shows a cross-sectional configuration diagram according to another embodiment of the present invention. In the figure, there is a diffusion layer 11a in which N-type impurities are diffused at a low concentration as a source and drain region in a part of a P-type semiconductor substrate 10, and a part of the diffusion layer 11a has an opening in an insulating film 12. The contact portion 12a is provided with a contact portion 12a, and even if the contact portion 12a has an opening area of the diffusion layer 11a cut to a depth of 0.2 μm, this cut contact portion 1
Diffusion layer ll in which N-type impurities are diffused at a high concentration around 2a
b, and the metal electrode 13 is connected to each contact portion 12.
It is in contact with the diffusion region 11b of the source and drain region through the a. In addition, in the same figure, 14 is the gate electrode, and as shown in Figure 4, the MOS transistor is miniaturized by making the impurity diffusion layer into low concentration and high concentration regions, and electrons are injected into the gate oxide film, resulting in the MOS transistor characteristics. Lightly Doped D prevents reliability deterioration
A rain-3 source (referred to as LDD) structure can be formed, and as in the first embodiment, the contact resistance can also be kept low, and miniaturization of transistors (MOS) can be realized.

In this Example 1.2, the case where the Si substrate is P ffa and the diffusion layer is N type is described, but there is no problem even if the conductivity type is reversed. Furthermore, in Example 1.2, when a Si substrate was used as the semiconductor substrate, the force < GaAs1In
Although similar effects can be obtained by using a P-based compound semiconductor substrate, etc., as is clear from the above explanation, according to the present invention, effective By widening the contact area, it is possible to prevent an increase in contact resistance. Furthermore, by providing a diffusion layer region having a depth equal to or greater than the depth of the groove on the outer periphery of the groove, an increase in junction leakage between the semiconductor substrate and the diffusion layer can be suppressed to a low level.

[Brief explanation of drawings]

FIG. 1 shows the cross-sectional configuration of a transistor portion of a semiconductor device according to an embodiment of the present invention. FIG. is a cross-sectional configuration diagram of a transistor section of a semiconductor device in a conventional example.

Claims (1)

[Claims] A semiconductor device including a diffusion layer formed in a part of a semiconductor substrate, an opening formed in a part of the diffusion layer, and an electrode in contact with a part of the diffusion layer through the opening, A semiconductor device having a groove extending inward of the diffusion layer directly below the opening, and having a diffusion layer region having a depth equal to or greater than the depth of the groove at the outer periphery of the groove.