JPH0335631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage generator used in, for example, an IC tester, and particularly aims to provide a voltage generator that has a simplified circuit structure and can be manufactured at low cost.

<Background of the Invention> For example, an IC tester tests ICs with different standards, so each time an IC with a different standard is tested, the drive voltage of the signal input to the IC under test,
A reference voltage must be set for determining whether the read output is H logic or L logic. Several types of each of these voltages must be prepared for each terminal of the IC under test. Furthermore, since the voltage must be controlled independently for each terminal, a large number of voltage generators are required. Therefore, it is impossible to manually set the voltages of each of these voltage generators. Conventionally, the set voltages are stored in a memory or the like in advance, and the data is read from this memory and converted from D to A. -A conversion output is used to obtain a desired set voltage. Since the number of D-A converters required is equal to the number of required set voltages, there is a disadvantage that the number increases and the cost increases.

However, as will be described later, in order to remove the offset voltage of a buffer amplifier, etc. that takes out the output of the D-A converter, offset data is stored for each voltage generator, and the offset data is used for D-A conversion. Then, the DA conversion output is subtracted from the set voltage. Therefore, there is a drawback that the number of DA converters increases.

<Conventional Description> FIG. 1 shows a conventional voltage generator. In this figure, only the part that generates one set voltage is shown. In the figure, 101 indicates a register that stores digital data corresponding to the voltage value to be output. Data 1 is stored in this register 101 from memory (not particularly shown).
02 is given and the data is stored. The data stored in the register 101 is given to a DA converter 103, where it is converted into an analog value. Since the D-A converter is generally a current output type, the D-A converter 103
A current-voltage converter 104 is provided on the output side of the signal to convert it into a voltage signal.

The output voltage of the current-voltage converter 104 is directly passed through the polarity inverter 105 to the polarity selection circuit 106.
supplied to The polarity selection circuit 106 is provided with two switches 106a and 106b, and these switches 106a and 106b select either positive or negative voltage according to the polarity data stored in the polarity data register 107, and select the selected polarity. is applied to the voltage adding circuit 108.

This voltage adder circuit 108 is provided to remove offset voltages generated in the buffer amplifier 109 and other analog circuits connected to the subsequent stage. In other words, buffer amplifier 1
If an offset voltage exists in the analog circuit after 09, the offset voltage will be added to the D-A conversion value of the setting voltage data stored in the register 101, and a voltage different from the voltage that should be given will be given as the setting value. It's inconvenient.

For this purpose, a correction circuit 111 generates a value equivalent to the offset voltage generated by the analog circuit after the buffer amplifier 109, and the correction voltage outputted from the correction circuit 111 is applied to the voltage addition circuit 108.
The offset voltage is removed.

The correction circuit 111 includes a register 112, a D-A converter 113, and a current - similar to the voltage generator described above.
The voltage conversion circuit 114 stores data 115 corresponding to the offset voltage value of the analog circuit previously measured in the register 112 from the memory, converts the data value from analog to analog, and supplies it to the voltage addition circuit 108. .

<Disadvantages of the conventional method> As mentioned above, in the conventional method, D-
In addition to requiring the A converter 103, the D-A converter 113 is also required for offset removal. As a result, the number of D-A converters increases, resulting in higher costs. Another drawback is that the circuit becomes larger and more complex.

<Objective of the Invention> The object of the present invention is to reduce costs by omitting the DA converter on the correction circuit 111 side and simplifying the circuit.

<Summary of the Invention> In the present invention, a value equivalent to an offset voltage is added or subtracted from the set voltage data in the state of a digital signal, and the value equivalent to the offset voltage is removed in the state of a digital signal, and the offset voltage is It is configured to perform DA conversion on a digital signal from which the corresponding value has been removed.

Therefore, according to the present invention, since one DA converter can be used in one channel, the number of DA converters can be reduced as a whole, and cost reduction can be expected.

<Embodiment of the Invention> FIG. 2 shows an embodiment of the invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this invention, for example, a data converter 201 capable of performing addition and subtraction operations according to polarity data is provided, and this data converter 20
1, a digital signal corresponding to the value of the most significant bit of the setting data 102 is added as an offset bias, and setting voltage data is added on the positive polarity side and subtracted on the negative polarity side around this offset bias. The device is configured to perform data conversion and convert the data-converted digital signal to DA conversion.

The operation of data converter 201 will be explained in more detail. Assuming that the set voltage data 102 given from the register 101 is, for example, 4-bit data, the register 112 configuring the correction circuit 111 outputs an offset bias "1, 0, 0, 0, 0”
give.

For this offset bias, register 101
If this data is positive polarity, the setting voltage data input from the data converter 20 is
1 performs an addition operation. Further, if the set voltage data has negative polarity, a subtraction operation is performed. The results of this addition and subtraction are shown in FIG. In FIG. 3, _B1 to _B5 indicate bit numbers, with _B5 indicating the MSB. As is clear from this figure, the upper side at the center of the offset bias 301 shows the value obtained by adding positive data to the offset bias 301, and the lower side shows the value obtained by adding positive data to the offset bias 301.
Indicates the value obtained by subtracting negative data from 01. Switching between the addition operation and the subtraction operation of the data converter 201 is performed by polarity data stored in the polarity data register 107.

The lower 4 bits _B1 to _B5 of this operation result are
−A converter 202; This DA converter 2
02 is the normal output terminal 202a and the complement output terminal 2
In this example, 4-bit digital data is DA-converted.

A current-voltage converter 104 is connected to the normal output terminal 202a of the DA converter 202, and a positive analog voltage is obtained from the current-voltage converter 104. Also, a resistor 203 is connected to the complement output terminal 202b.
A current-voltage converter 104' constructed by the above resistor 203 is connected to obtain a negative analog voltage generated by the current flowing through the resistor 203.

The positive and negative analog voltages outputted from these current-voltage converters 104 and 104' are applied to the polarity selection circuit 106, and either the positive or negative analog voltage is taken out from the polarity selection circuit 106, and the buffer amplifier 109 The analog voltage is outputted to the output terminal 110 through. Switches 106a and 106b of the polarity selection circuit 106 are connected to the data converter 20.
It is controlled on/off by the logic of the most significant bit _B5 output from 1. In other words, adder/subtractor 201
When the most significant bit _B5 output from the circuit is logic "1", the switch 106a is turned on and a positive analog voltage is taken out. Also, the most significant bit B ₅
When the logic is "0", the switch 106b is turned on and a negative analog voltage is taken out.

The relationship between the normal output terminal 202a and the complement output terminal 202b of the DA converter 202 is as shown in FIG. In FIG. 4, 401a,
401b, 401c, and 401b are switches each controlled by a digital signal. Terminals 402a, 402b, 402c, 402
A digital signal is applied to d. Terminal 402a
is the LSB, and the terminal 402d is the MSB. When L logic is applied to each of these terminals 402a to 402d, the switches 401a to 401d switch to the contact a side, and when H logic is applied to each terminal 402a to 402d, the switches 401a to 401
d is controlled to switch to the contact b side.

Therefore, if all the digital signals at the terminals 402a to 402d are L logic, the normal output terminal 202
The current flowing through a is zero. On the other hand, all the current sources 403a and 40 are connected to the complement output terminal 202b.
3b, 403c, 403d all currents I, 2I,
4I and 8I are added and flow. When only the terminal 402a becomes H logic, the switch 401a changes to contact b and outputs the current I of the current source 403a to the normal output terminal 202a. Along with this, the complement output terminal 203
The current of b is (2I+4I+8I). In this way, the output currents of the normal output terminal 202a and the complement output terminal 202b change complementary to each other.

FIG. 5 shows the relationship between digital data and analog output. In the digital data shown in Figure 5, the bit marked with a box is the MSB.
The polarity selection circuit 106 is controlled by the logic.

The case where the buffer amplifier 109 has an offset voltage will now be explained. To measure the offset voltage, set the register 101 to “0, 0, 0,
The data of "0" is stored, and the digital data of "0, 0, 0, 0" is subjected to DA conversion in the DA converter 202. This DA conversion output is given to buffer amplifier 109, and the voltage at output terminal 110 is measured. The voltage output to the output terminal 110 at this time is the offset voltage.

The offset bias value stored in the register 112 is finely adjusted so that this offset voltage becomes zero. For example, if an offset voltage of +1 mV occurs, the value of the offset bias is changed to cancel that value. In other words, the offset bias can be changed from "1, 0, 0, 0, 0" to, for example, "0,
1, 1, 1, 0”.

Furthermore, if the offset voltage is, for example, -1 mV, the value of the offset bias is set to "1, 0, 0, 0,
1”.

<Effects of the Invention> As described above, according to the present invention, the offset voltage can be removed by changing the offset bias in the state of the digital signal. Therefore, D-A used in one voltage generation circuit
Since the number of converters can be reduced to one, cost reduction can be expected.

<Other embodiments of the invention> In the above description, one voltage generator is configured by one D-A converter 202.
As shown in FIG. 6, a day multiplexer 601 is provided on the output side of the buffer amplifier 109, and the day multiplexer 601 distributes the output voltage of the buffer amplifier 109 to a plurality of sample and hold circuits 602a, 602b, ... 602n. By sequentially rewriting each data stored in the registers 101, 107, and 112 into the data required for each channel in synchronization with distribution, a single D-A converter 202 can output voltages for multiple channels. can be expected to further reduce costs.

In FIG. 6, reference numeral 603 indicates a timing generator, and the setting voltage data, polarity data, and offset bias data of each channel read out from the memory by the timing signal outputted from the timing generator 603 are stored in the registers 101 and 10.
7 and 112 in sequence. Also, these registers 101, 109, and 112 are each
A RAM-like memory is used, and the data of each channel is directly output from this memory to the data converter 2.
It can also be configured to be given to 01.

In the above description, the data converter 201 has been described as an adder/subtracter, but as another method, the data converter circuit 201 can be configured by a circuit that outputs positive data as is and converts negative data into its complement.

An example is shown in FIG. 70 in Figure 7
1 indicates buffer. This buffer 701 is given polarity data. 702a, 702b, 702
c and 702d each indicate an exclusive OR circuit. Polarity data is applied to one input terminal of each of these exclusive OR circuits 702a to 702d, and setting voltage data is applied to the other input terminal.

Therefore, in the case of positive polarity data, "1" logic is applied to one input terminal of each of the exclusive OR circuits 702a to 702d, so that the set voltage data is output with the same logic. In addition, in the case of negative polarity data, each exclusive OR circuit 702a to 702d
Since a logic "0" is applied to each one of the input terminals, the set voltage data is inverted to the opposite logic, converted to a complement, and output. The logic converted to this complement is the offset bias 3 shown in Figure 3.
This corresponds to the logic of bits _B1 to _B4 shown below 01.

In this way, the data converter 201 can be configured not only by an addition/subtraction circuit but also by a circuit that converts input data into a complement number according to polarity data.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining a conventional voltage generator, FIG. 2 is a block diagram for explaining an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of the present invention, and FIG. 4 is a block diagram for explaining a conventional voltage generator. is a connection diagram showing an example of a D-A converter used in the voltage generator of this invention, FIG. 5 is a graph for explaining the operation of this invention, and FIG. 6 shows another embodiment of this invention. The block diagram in FIG. 7 is a connection diagram showing another example of the data converter used in the present invention. 201: Data converter, 202: DA converter, 106: Polarity selection circuit.

Claims (1)

[Claims] 1 A Data that defines the voltage value to be output and polarity data that defines the polarity of the voltage to be output;
An offset bias value is input, and for input data of one polarity, the input data and offset data are added, and for input data of the other polarity, the input data is subtracted from the offset bias and output. , B converts the output data of this adder/subtractor into a D-A converter and has a normal output terminal and multiple output terminals; C selects the output of the normal output terminal and multiple output terminals based on the polarity data. A voltage generator comprising: a selection switch for taking out the voltage;