JPH0337541U - - Google Patents
Info
- Publication number
- JPH0337541U JPH0337541U JP9749989U JP9749989U JPH0337541U JP H0337541 U JPH0337541 U JP H0337541U JP 9749989 U JP9749989 U JP 9749989U JP 9749989 U JP9749989 U JP 9749989U JP H0337541 U JPH0337541 U JP H0337541U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- main control
- transmitted
- output device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
Description
第１図はこの発明の一実施例に係るインタフエ
ースの故障検出回路の構成を示すブロツク図、第
２図は第１図の回路の動作を示すタイミングチヤ
ート、第３図は複合端末装置の構成を示すブロツ
ク図、第４図はメイン制御部とプリンタとのイン
タフエースの構成図、第５図は第４図の装置の動
作を示すタイミングチヤート、第６図は第４図の
インタフエースに異常が生じた場合の説明図、第
７図は第６図の状態での動作を示すタイミングチ
ヤートである。
図において、２はメイン制御部、５はプリンタ
、２１はＢＵＳＹ信号変化検出器、２２は
信号変化検出器、２３は信号
オン検出器、２６はプリンタインタフエース制御
回路である。
FIG. 1 is a block diagram showing the configuration of an interface failure detection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the circuit in FIG. 1, and FIG. 3 is the configuration of a composite terminal device. Fig. 4 is a block diagram showing the interface between the main control unit and printer, Fig. 5 is a timing chart showing the operation of the device shown in Fig. 4, and Fig. 6 shows an abnormality in the interface shown in Fig. 4. FIG. 7 is a timing chart showing the operation in the state shown in FIG. 6. In the figure, 2 is a main control section, 5 is a printer, 21 is a BUSY signal change detector, 22 is a signal change detector, 23 is a signal-on detector, and 26 is a printer interface control circuit.
Claims (1)
が行なわれた後に該出力装置のデータ受信処理の
有無を監視する回路と、 メイン制御部からのデータ送信後、出力装置の
データ受信処理がない状態で次のデータが送信さ
れた場合に、メイン制御部に対してデータ転送を
停止させる回路と を有することを特徴とするインタフエースの故障
検出回路。[Claims for Utility Model Registration] A circuit for monitoring whether or not the output device is receiving data after data is transmitted from the main control section to the output device; 1. A failure detection circuit for an interface, comprising: a circuit for causing a main control unit to stop data transfer when the next data is transmitted without data reception processing being performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9749989U JPH0337541U (en) | 1989-08-23 | 1989-08-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9749989U JPH0337541U (en) | 1989-08-23 | 1989-08-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0337541U true JPH0337541U (en) | 1991-04-11 |
Family
ID=31646637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9749989U Pending JPH0337541U (en) | 1989-08-23 | 1989-08-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337541U (en) |
-
1989
- 1989-08-23 JP JP9749989U patent/JPH0337541U/ja active Pending
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