JPH0338632U - - Google Patents
Info
- Publication number
- JPH0338632U JPH0338632U JP9939889U JP9939889U JPH0338632U JP H0338632 U JPH0338632 U JP H0338632U JP 9939889 U JP9939889 U JP 9939889U JP 9939889 U JP9939889 U JP 9939889U JP H0338632 U JPH0338632 U JP H0338632U
- Authority
- JP
- Japan
- Prior art keywords
- electrode portion
- metallized
- plating
- plating electrode
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007747 plating Methods 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の半導体パツケージ
用配線基板を示す図、第２図は第１図に示した半
導体パツケージ用配線基板の断面図である。
１…セラミツクス多層基板、２…ダイパツド、
３…ボンデイングパツド、４…シールリング接合
部、５…リードパツド、６ａ，６ｂ…めつき用電
極部、７ａ，７ｂ…内部配線、８ａ，８ｂ…スル
ーホール。
FIG. 1 is a diagram showing a wiring board for a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a sectional view of the wiring board for a semiconductor package shown in FIG. 1... Ceramics multilayer substrate, 2... Die pad,
3... Bonding pad, 4... Seal ring joint part, 5... Lead pad, 6a, 6b... Electrode part for plating, 7a, 7b... Internal wiring, 8a, 8b... Through hole.
Claims (1)
合するための、個々に独立した複数のメタライズ
部と、 これらメタライズ部にめつきを施すために前記
セラミツクス基板に少なくとも ２つ以上配設さ
れためつき用電極部と、 前記メタライズ部のうち同一条件でめつきを行
うメタライズ部同士が一括して前記めつき用電極
部に電気的に接続され、かつ、前記めつき用電極
部ごとに電気的に独立している複数のめつき用配
線パターンと、 を備えたことを特徴とする半導体パツケージ用
配線基板。[Claims for Utility Model Registration] A plurality of individually independent metallized parts for joining parts formed on the surface of a ceramic substrate, and at least two metallized parts on the ceramic substrate for plating these metallized parts. The plating electrode portion arranged as described above and the metallized portions that are plated under the same conditions among the metallized portions are collectively electrically connected to the plating electrode portion, and the plating electrode portion is electrically connected to the plating electrode portion. A wiring board for a semiconductor package, comprising: a plurality of wiring patterns for plating that are electrically independent for each part;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9939889U JPH0338632U (en) | 1989-08-24 | 1989-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9939889U JPH0338632U (en) | 1989-08-24 | 1989-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338632U true JPH0338632U (en) | 1991-04-15 |
Family
ID=31648455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9939889U Pending JPH0338632U (en) | 1989-08-24 | 1989-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338632U (en) |
-
1989
- 1989-08-24 JP JP9939889U patent/JPH0338632U/ja active Pending