JPH0338727A - Resources interference controller and data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device controlled by a pipeline control method that processes multiple instructions in parallel. The present invention relates to a data processing device in which a compiler generates information for controlling resource interference between resources at the time of compilation, and minimizes the cost for controlling the resource interference as hardware.

2. Description of the Related Art As a device for controlling resource interference between instructions executed by conventional pipeline control, "Interface J (
June 1987 issue, P348-350) “Mips R
ISC' Architecture J (Plenti
ce Hall Publishing, 1988).

FIG. 2 shows the configuration of the above-mentioned conventional data processing device. As shown in the figure, 1 is the main memory, 2 is the external interface, 3 is the arithmetic unit, 4 is the instruction register, 5 is the decoder, 6 is the decoder register, 7 is the external bus, 8 is the internal bus for instructions, 9
is an internal bus for data.

The operation of the conventional data processing apparatus configured as described above will be explained. FIG. 3 is a timing diagram showing the operation. In Figure 3, IF is an instruction fetch, DEC is an instruction decoder, EX is an operation, W is a result write, and M is an external cycle stage (the basic processing unit of pipeline processing). tl.

I2. ...I7 is the passage of time, ■1. Engineering 2. ~Step 4 indicates a sequence of instructions to be processed. At time I4,
I no IF, I no DEC, I, no EX, I,
(7) Four instructions are processed in parallel at each stage of 4 3 W.

The RR operation instruction performs an operation between registers within the operation unit 3. The load instruction performs a data transfer operation from the main memory 1 to a register within the operation unit 3.

Instruction sequence 11. I2,1. ,I. Nifu Teiko is the load command, ■. When is an RR operation instruction, the registers used by the instruction are limited to those that are not affected by the execution of instruction I2.

The instruction string stored in the main memory 1 is transferred to the instruction register 4 via an external bus 7, an external interface 2, and an internal instruction bus 8. The instructions stored in the instruction register 4 are decoded by the decoder 5, converted into information for controlling the arithmetic unit 3, and stored in the decoder register 6.

In Fig. 3, the instructions are shown. is a register in which data transferred from main memory 1 by instruction I2 is stored.

However, it operates after waiting for the end of the external cycle stage (M), and in this case, the instructions after the instruction are not limited to the registers used, and the instructions immediately after the instruction are By adjusting the registers used by the instructions by the compiler, parallel execution by pipeline processing can be realized without contradiction.

Problems to be Solved by the Invention However, in the more advanced method described in ``2'', it is necessary for the combiner to generate an instruction immediately after the external cycle instruction that does not require the register in which this external cycle instruction is stored. If an appropriate instruction sequence cannot be scheduled, an invalid operation (
This method has problems such as the need to insert a nop instruction and the need to move unnecessary instructions from the main memory.

In view of this, the present invention provides the following steps to avoid interference with resources required by preceding instructions in the instruction format.
By using an instruction system that allows the compiler to calculate information regarding the timing at which resource interference is removed and embed this information directly into instructions, a low-cost data processing device that does not require fetching of unnecessary instructions can be created. The purpose is to provide.

Means for Solving the Problems The present invention provides a means for decoding an instruction system including an instruction format having a specific field in which information regarding the previous delay interval for executing the instruction can be set in the instruction word after the instruction word is decoded. and has information regarding the delay time described above."2. If a subsequent instruction requires the execution result of one or more preceding instructions, the instruction is executed according to the set information. By delaying the information set in the specific field of this instruction word, the data processing device and the result of the preceding instruction are enabled with the motive of avoiding resource interference between the preceding instruction and the following instruction. An instruction that has an instruction system that allows timing-related information to be set in the following instruction word, and that, after decoding the instruction, precedes the operation on the register, etc. that is the target of the operation such as the arithmetic processing specified by this instruction. means for extracting and storing information in the command word for delaying the instruction by a time determined depending on the type of the instruction, or by a time when a synchronization signal sent from the memory device or the input/output device is valid;
This resource interference control foil production is equipped with means for measuring a determined time or detecting the synchronization signal according to this information.

According to the present invention, when the execution result of the preceding instruction is required by the subsequent instruction, information regarding this is incorporated into the subsequent instruction word, thereby improving the performance in pipeline processing. It is possible to reduce the hardware cost in controlling resource interference between instructions.

Embodiment FIG. 1 is a block diagram of a data processing apparatus in an embodiment of the present invention.

In FIG. 1, 10 is a main memory, 20 is an external interface, 30 is an arithmetic unit, 40 is an instruction register, 50 is a decoder, 60 is a decoder register, 7o is an external bus, 80
1 is an internal bus for instructions, 90 is an internal bus for data, 100 is a delay control circuit, 110 is a delay synchronization control circuit, 120 is a synchronization signal, and 130, 131, 140, and 140 are delay control signals.

FIG. 4 is an explanatory diagram of the command word format according to the embodiment of FIG. 1. The button ○P in FIG. 4 is a field that defines a function specific to the command. RA, RB.

RC is a field that defines the operand that is the target of the operation, RA is the first source operand, RB is the second source operand, and RC is the destination that stores the result obtained by processing the first and second source operands. Indicates the nation operand. DC is a field that defines information regarding execution delay time when resource interference occurs in relation to a preceding instruction, which is the core of the present invention.

FIGS. 5 and 6 are timing charts showing the operation of the first embodiment. In FIGS. 5 and 6, buttons indicate the following stages: IF indicates instruction processing, DEC indicates instruction decoding, Ex indicates operation execution, W indicates operation result storage, MO indicates internal multi-cycle execution, and Ml indicates external multi-cycle execution. Box t1~
t8 is a time series of machine cycles, and t8 and t8 are instruction sequences.

The operation of the i-event processing apparatus according to the embodiment of the present invention, which has been intercepted as described above, will be explained below.

I, , I, , 1 in FIG. In the instruction sequence I,,I.

2 is a 1-cycle RR operation instruction, and 2 is a 2-cycle multicycle/1/R-R operation instruction.

Command line engineer, ~ engineer. are sequentially transferred to the instruction register 40 through the main memory 10, external bus 70, external interface 20, and internal instruction bus 80. The instruction sequence is processed in the decoding, execution, and storage stages.

Figure 5 shows ■. This shows a case in which the execution result of the preceding command is required. , is a two-cycle instruction, so it is an instruction that is read later. requires a one-cycle delay in execution. At the time the instruction code is decoded and the decoding result is stored in the decoder register 60. The information in the control field (DC) is transferred to the delay control circuit 100 through the signal line 141, and the execution of the arithmetic unit 1-30 in the next cycle is prohibited by sending out the signal line 140; , to avoid resource interference by extending the execution stage (EX) of .

Instruction sequences I, , I, , I in FIG. In, 11. I3
゜■ is a one-cycle R-R operation instruction, and ■ is a load instruction that requires multiple cycles.

The instruction strings (1) to (4) stored in the main memory 10 are sequentially fetched and processed at the timing shown in FIG. 6th
The illustration is by engineering. The execution result of the instruction preceded by 0 (i.e., the read data from the main memory 10 in this case)
Indicates when you need it. Engineering.

is a load instruction that requires multiple cycles, and the execution cycle must be synchronized with the speed of the main memory 10.

Command engineer. When )Il/me is decoded and stored in the read register 60, the delay control field of instruction ■4)vdo(DC
) information is sent to the delay synchronization control circuit 11 through the signal line 131.
Transferred to 0 and ordered. Execution of external interface 2
When the synchronization signal 120 sent from O is enabled, the execution of the execution unit 30 is prohibited by sending the signal line 130. Extend the execution stage (EX) to avoid resource interference.

As described above, according to the embodiment of the present invention, when a later instruction requires the execution result of a preceding instruction, information such as the waiting time and queuing event related to resource interference is incorporated into the later instruction word. , Reducing the hardware cost of the device 1'R for avoiding resource interference between instructions in pipeline processing, and eliminating unnecessary instruction fuss and overhead associated with the method of introducing invalid instructions into the instruction sequence. Furthermore, it is possible to compress the instruction code size.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when a subsequent instruction requires the execution result of a preceding instruction, information regarding the waiting time, queuing event, etc. related to resource interference is incorporated into the subsequent instruction word. As a result, a high-speed, low-cost data processing device that performs pipeline processing can be realized, and its practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention;
FIG. 2 is a configuration diagram of a conventional data processing device, FIG. 3 is a timing diagram explaining the operation of the conventional data processing device, and FIG.
The figure is an explanatory diagram of the command word format in the embodiment of the present invention.
6 are timing charts for explaining the operation of the same embodiment. 10... Main memory, 20... External interface, 30... Arithmetic unit, 40...
...Instruction register, 50...Decoder, 60.
... Decoder register, 70 ... External bus, 80 ... Internal bus for instructions, 90 ... Internal bus for data, 100 ... Delay control circuit, 1
10... Delay synchronization control circuit, 120...
・Synchronization signal, 130,131.140,141 ・・−
...Delay control signal.

Claims (2)

[Claims] (1) When a subsequent instruction requires the execution result of a preceding instruction, the waiting time for the preceding instruction is included in the subsequent instruction code.
A decoder that decodes an instruction code into which information consisting of a waiting event can be incorporated, and a preceding instruction that, after decoding the instruction, uses the incorporated information to operate the resource that is the target of the operation such as arithmetic processing specified by this instruction. The time determined by the type of
Or, in order to delay the execution of a subsequent instruction until the time when a signal sent from a memory device or an input/output device becomes valid, a means for extracting the necessary information from the instruction code, and a method for measuring a time determined according to this information, or A resource interference control device comprising the above-mentioned means for detecting the transmitted signal. (2) A means for decoding an instruction system that has a specific instruction field for setting information on the delay time until execution in the instruction word after decoding the instruction, and a means for deciphering an instruction system that has a specific instruction field for setting information about the delay time until execution in the instruction word, and a method for setting the execution of the instruction in a specific field of the instruction word. means for delaying by information;
When the lookbehind instruction does not require the result of the preceding instruction,
A data processing device equipped with means for executing a read-behind instruction without waiting for the completion of a preceding instruction.