JPH0338745B2 - - Google Patents

Info

Publication number
JPH0338745B2
JPH0338745B2 JP59071654A JP7165484A JPH0338745B2 JP H0338745 B2 JPH0338745 B2 JP H0338745B2 JP 59071654 A JP59071654 A JP 59071654A JP 7165484 A JP7165484 A JP 7165484A JP H0338745 B2 JPH0338745 B2 JP H0338745B2
Authority
JP
Japan
Prior art keywords
heat sink
groove
power element
power transistor
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59071654A
Other languages
Japanese (ja)
Other versions
JPS6065538A (en
Inventor
Kikuo Isoyama
Akira Kazami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP59071654A priority Critical patent/JPS6065538A/en
Publication of JPS6065538A publication Critical patent/JPS6065538A/en
Publication of JPH0338745B2 publication Critical patent/JPH0338745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/353Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明はヒートシンクの製造方法、特に混成集
積回路等に用いるヒートシンクの製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a heat sink, and particularly to a method for manufacturing a heat sink used for hybrid integrated circuits and the like.

(ロ) 従来技術 従来の混成集積回路は第1図に示す如く、セラ
ミツクスあるいは表面を陽極酸化したアルミニウ
ム等の絶縁基板1と、該基板1上に任意の形状に
設けた導電路2と、該導電路2上に半田で固着さ
れたヒートシンク3と、ヒートシンク3に固着さ
れたパワートランジスタ4と、パワートランジス
タ4を被覆保護する封止樹脂層5と、基板1の周
端に接着シート6で接着され全体を覆う蓋体7と
で構成されていた。
(b) Prior Art As shown in FIG. 1, a conventional hybrid integrated circuit includes an insulating substrate 1 made of ceramics or aluminum whose surface is anodized, a conductive path 2 provided in an arbitrary shape on the substrate 1, and a conductive path 2 provided in an arbitrary shape on the substrate 1. A heat sink 3 fixed on the conductive path 2 with solder, a power transistor 4 fixed on the heat sink 3, a sealing resin layer 5 covering and protecting the power transistor 4, and bonded to the peripheral edge of the substrate 1 with an adhesive sheet 6. and a lid body 7 that covers the entire body.

斯る構造の混成集積回路はテレビ、ラジオ、ス
テレオ等の比較的良好な使用環境を有する電子機
器では十分な封止と評価されていた。しかしなが
ら自動車の電装部品等の如く極めて使用環境の悪
いものにおいては十分な封止構造とはいえず、特
に電力を消費するパワートランジスタの劣化が極
めて問題となつていた。即ちヒートサイクルの結
果、封止樹脂層5にクラツクが発生し、クラツク
から入る酸素により半田酸化が起こり、パワート
ランジスタ4とヒートシンク3との熱抵抗が増大
してパワートランジスタ4が二次破壊されるので
ある。
Hybrid integrated circuits with such a structure have been evaluated as having sufficient sealing for electronic equipment such as televisions, radios, stereos, etc. that have relatively favorable usage environments. However, it cannot be said that the sealing structure is sufficient for items such as electrical components of automobiles, which are used in extremely poor environments, and deterioration of power transistors, which consume electric power, has become a serious problem. That is, as a result of the heat cycle, cracks occur in the sealing resin layer 5, solder oxidation occurs due to oxygen entering through the cracks, and the thermal resistance between the power transistor 4 and the heat sink 3 increases, resulting in secondary destruction of the power transistor 4. It is.

(ハ) 発明の目的 本発明は斯点に鑑みてなされ、混成集積回路に
組み込むパワートランジスタの良好な封止構造を
実現するヒートシンクの簡便な製造方法を提供す
ることを目的とする。
(c) Object of the Invention The present invention was made in view of the above, and an object of the present invention is to provide a simple method for manufacturing a heat sink that realizes a good sealing structure for a power transistor incorporated into a hybrid integrated circuit.

(ニ) 発明の構成 本発明に依れば、平板上のヒートシンク上面に
溝を形成し、該溝の内側端部をプレスして逆テー
パー面を形成する様に構成されている。
(d) Structure of the Invention According to the present invention, a groove is formed on the upper surface of the heat sink on a flat plate, and the inner end of the groove is pressed to form a reverse tapered surface.

(ホ) 実施例 本実施例に依れば第2図Aに示す如く、13mm角
で厚さ3mmの銅片より成る平板状のヒートシンク
13を準備する。ヒートシンク13の上面には第
2図Bに示す如く、周辺に連続してあるいは不連
続して溝19をプレスにより形成する。溝19は
巾500μm、深さ300μm程度の逆台形状に形成さ
れる。続いて第2図Cに示す如く、溝19の内側
端部を部分的に平プレスしてプレスによる変形を
利用して逆テーパー面18を形成する。
(E) Embodiment According to this embodiment, as shown in FIG. 2A, a flat heat sink 13 made of a copper piece 13 mm square and 3 mm thick is prepared. As shown in FIG. 2B, grooves 19 are formed on the upper surface of the heat sink 13 by pressing, either continuously or discontinuously around the periphery. The groove 19 is formed in an inverted trapezoid shape with a width of about 500 μm and a depth of about 300 μm. Subsequently, as shown in FIG. 2C, the inner end of the groove 19 is partially flat-pressed to form a reverse tapered surface 18 by utilizing the deformation caused by the pressing.

なお逆テーパー面18は溝19の内側斜面でも
外側斜面でも形成して良い。
Note that the reverse tapered surface 18 may be formed on either the inner slope or the outer slope of the groove 19.

斯上した本発明に依るヒートシンク13は第3
図に示す如く、混成集積回路に組み込まれる。混
成集積回路はセラミツクスあるいは表面を陽極酸
化したアルミニウム等の絶縁基板11と、該基板
11上に任意の形状に設けた銅箔より成る導電路
12と、導電路12上に半田で固着されたヒート
シンク13と、ヒートシンク13上に固着したパ
ワートランジスタ14と、本考案の特徴とする溝
19と、パワートランジスタ14を被覆する封止
樹脂層15より構成されている。
The heat sink 13 according to the present invention described above is the third heat sink 13 according to the present invention.
As shown in the figure, it is incorporated into a hybrid integrated circuit. The hybrid integrated circuit includes an insulating substrate 11 made of ceramics or aluminum whose surface is anodized, a conductive path 12 made of copper foil provided in an arbitrary shape on the substrate 11, and a heat sink fixed on the conductive path 12 with solder. 13, a power transistor 14 fixed on the heat sink 13, a groove 19 which is a feature of the present invention, and a sealing resin layer 15 covering the power transistor 14.

パワートランジスタ14はヒートシンク13の
溝19の内側に半田で固着され、エポキシ樹脂等
の封止樹脂層15を塗布してパワートランジスタ
14を被覆して保護する。この際封止樹脂層15
は溝19内にも充填される。その結果、ヒートシ
ンク13に溝19に逆テーパー面が形成されてい
るためにヒートサイクルによつて封止樹脂層に応
力が加わつたとしても逆テーパー面がもどり形状
になつているために封止樹脂層の剥離を防止する
ことができる。
The power transistor 14 is fixed to the inside of the groove 19 of the heat sink 13 with solder, and a sealing resin layer 15 such as epoxy resin is applied to cover and protect the power transistor 14. At this time, the sealing resin layer 15
is also filled in the groove 19. As a result, since the groove 19 of the heat sink 13 has an inverted tapered surface, even if stress is applied to the sealing resin layer due to heat cycles, the inverted tapered surface returns to its shape, so the sealing resin Peeling of layers can be prevented.

(ヘ) 発明の効果 本発明に依ればヒートシンク13に逆テーパー
面18を2回のプレス工程で容易に形成できる利
点を有する。そして混成集積回路に組み込めばヒ
ートサイクルに強いパワートランジスタ14の封
止構造を実現できる。
(F) Effects of the Invention According to the present invention, there is an advantage that the reverse tapered surface 18 can be easily formed on the heat sink 13 by two press steps. If it is incorporated into a hybrid integrated circuit, a sealed structure for the power transistor 14 that is resistant to heat cycles can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の混成集積回路を説明する断面
図、第2図A,B,Cは本発明のヒートシンクの
製造方法を説明する断面図、第3図は本発明のヒ
ートシンクを用いた混成集積回路を説明する断面
図である。 主な図番の説明、13はヒートシンク、19は
溝、18は逆テーパー面である。
FIG. 1 is a cross-sectional view explaining a conventional hybrid integrated circuit, FIGS. 2 A, B, and C are cross-sectional views explaining the method of manufacturing the heat sink of the present invention, and FIG. 3 is a cross-sectional view of a hybrid integrated circuit using the heat sink of the present invention. FIG. 2 is a cross-sectional view illustrating a circuit. Explanation of the main figure numbers: 13 is a heat sink, 19 is a groove, and 18 is a reverse tapered surface.

Claims (1)

【特許請求の範囲】 1 パワー素子のみが固着され、且つ、前記パワ
ー素子を封止する封止樹脂がその上面に配置され
る平板状のヒートシンクの製造方法において、 前記平板状のヒートシンク上に前記パワー素子
が固着される周辺近傍に、前記パワー素子を取り
囲むように溝を形成し、 前記パワー素子を取り囲む前記溝の内側端部を
プレスして逆テーパー面を形成することを特徴と
するヒートシンクの製造方法。
[Scope of Claims] 1. A method for manufacturing a flat heat sink in which only a power element is fixed, and a sealing resin for sealing the power element is placed on the top surface, comprising: A heat sink characterized in that a groove is formed near the periphery to which the power element is fixed so as to surround the power element, and an inner end of the groove surrounding the power element is pressed to form a reverse tapered surface. Production method.
JP59071654A 1984-04-10 1984-04-10 Heat sink manufacturing method Granted JPS6065538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59071654A JPS6065538A (en) 1984-04-10 1984-04-10 Heat sink manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59071654A JPS6065538A (en) 1984-04-10 1984-04-10 Heat sink manufacturing method

Publications (2)

Publication Number Publication Date
JPS6065538A JPS6065538A (en) 1985-04-15
JPH0338745B2 true JPH0338745B2 (en) 1991-06-11

Family

ID=13466807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59071654A Granted JPS6065538A (en) 1984-04-10 1984-04-10 Heat sink manufacturing method

Country Status (1)

Country Link
JP (1) JPS6065538A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128279A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Heat sink for resin-sealed semiconductor device and its manufacture

Also Published As

Publication number Publication date
JPS6065538A (en) 1985-04-15

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