JPH0338904A - One output differential amplifier - Google Patents
One output differential amplifierInfo
- Publication number
- JPH0338904A JPH0338904A JP17459489A JP17459489A JPH0338904A JP H0338904 A JPH0338904 A JP H0338904A JP 17459489 A JP17459489 A JP 17459489A JP 17459489 A JP17459489 A JP 17459489A JP H0338904 A JPH0338904 A JP H0338904A
- Authority
- JP
- Japan
- Prior art keywords
- output
- differential amplifier
- current source
- constant current
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＦＥＴを用いたー出力差動増幅器に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an output differential amplifier using FETs.
従来、この種の差動増幅器は、ダミー出力を開放してい
た。倒えば、信学技報（ＳＳＤ８５−１１５）「ＧａＡ
ｓモノリシック・フロントエンドＩＣの試作」参照。Conventionally, this type of differential amplifier has had a dummy output open. If it falls, IEICE Technical Report (SSD85-115) “GaA
s Monolithic Front-End IC Prototype”.
上述した従来の差動増幅器は、ゲート長０．８μｍのＦ
ＥＴの場合、その周波数特性が利得３ｄＢ低下の周波数
にかいて、３ＧＨｚ程度と低かった。The conventional differential amplifier described above has a gate length of 0.8 μm.
In the case of ET, its frequency characteristics were as low as about 3 GHz at a frequency where the gain was reduced by 3 dB.
本発明の目的は、このような問題を解決し、周波数特性
を高周波域筐で延長したー出力差動増幅器を提供するこ
とにある。An object of the present invention is to solve such problems and provide an output differential amplifier with extended frequency characteristics in a high frequency range housing.
本発明の一出力差動増幅器の構成は、定電流源のトラン
ジスタを有する一対の差動トランジスタと、この差動ト
ランジスタの各出力をそれぞれ取出す二組の出力回路と
、この出力回路の一方をダミー出力としここから前記定
電流源のトランジスタに一方の出力信号を供給するフィ
ードフォワード回路とを備え、前記出力回路の他方から
出力信号を取出すととｆ：％微とする。The configuration of the one-output differential amplifier of the present invention includes a pair of differential transistors each having a constant current source transistor, two sets of output circuits that take out each output of the differential transistors, and one of the output circuits as a dummy. A feedforward circuit is provided for supplying one output signal from the output circuit to the transistor of the constant current source, and when an output signal is taken from the other output circuit, it is assumed that f: % fine.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.
本実施例は、ゲート幅５０μｍ、ゲート長０．８μｍの
ＦＥＴＱｌ−Ｑ畠と、ゲート幅５０μｍのダイオードＤ
１〜Ｄ６と、コンデンサＣ１，抵抗Ｒ１。This example uses a FET Ql-Q Hatake with a gate width of 50 μm and a gate length of 0.8 μm, and a diode D with a gate width of 50 μm.
1 to D6, capacitor C1, and resistor R1.
Ｒｓ、負荷抵抗Ｒｓ、Ｒ４とから構成されている。Rs, load resistance Rs, and R4.
信号入力端ＩＮ、ＩＮ からは１８０’ 位相差があ
う同振幅の入力信号がそれぞれ入力される。これら入力
信号が各々ＦＥＴＱ１．Ｑｔによって増幅され、さらに
各信号はアイソレーシーンをとるためにＦ Ｅ Ｔ Ｑ
ａ 、ダイオードＤｓ 、 Ｄｓ 、 Ｄｓ 、ＦＥ
ＴＱｓ及びＦＥＴＱｓ、ダイオードＤ’ ＋ Ｄｓ ＋
Ｄ Ｂ ＊ＦＥＴＱ、 によるソースフォログ回路
を通す。Input signals having the same amplitude with a 180' phase difference are input from the signal input terminals IN and IN, respectively. These input signals are applied to each FETQ1. Qt, and each signal is further amplified by FETQ to take an isolating scene.
a, diode Ds, Ds, Ds, FE
TQs and FETQs, diode D' + Ds +
D B *FETQ, passes through the source follower circuit.
この回路の前者を出力、後者をダミー出力とすると、ダ
ミー出力をコンデンサＣＩ、抵抗Ｒ１を介して、差動増
幅器内の定１ｉＥｆｌＬ源ＦＥＴＱｓに供給する。If the former of this circuit is an output and the latter is a dummy output, the dummy output is supplied to the constant 1iEflL source FETQs in the differential amplifier via the capacitor CI and the resistor R1.
この場合、フィードフォワードの周波数特性は、コンデ
ンサＣ１の容量値に依存し、ツイードフォワード量は、
抵抗Ｒ１，Ｒｓの抵抗値に依存する。In this case, the feedforward frequency characteristics depend on the capacitance value of capacitor C1, and the tweedforward amount is
It depends on the resistance values of the resistors R1 and Rs.
ここで、Ｒ１を２０Ω、Ｒ１を４０Ω、Ｃ１を２１）Ｆ
ｔ電源■ＤＤを＋５Ｖ、 Ｖｓｓを一５Ｖ トスル、
！−。Here, R1 is 20Ω, R1 is 40Ω, C1 is 21)F
t Power supply ■ DD +5V, Vss -5V tossle,
! −.
従来例では３ｄＢ低下の周波数が３ＧＨｚであったもの
が本実施例では５ＧＨｚ と高周波域に延長されてい
る。In the conventional example, the frequency of 3 dB reduction was 3 GHz, but in this embodiment, it is extended to 5 GHz, a high frequency range.
以上説明した様に、本発明の差動増幅器は、ダミー出力
を差動増幅器内の定電流源にフィードフォワードを施す
ことにより、周波数帯域特性を大幅に高周波域まで改善
する効果がある。As described above, the differential amplifier of the present invention has the effect of significantly improving frequency band characteristics up to high frequencies by feeding forward the dummy output to the constant current source within the differential amplifier.
第１図は本発明の一実施例の回路図である。
ＣＩ・・・・・・キャパシタ、Ｑ１〜Ｑ？・・・・・・
ＦＥＴ。
Ｄｌ −Ｄ・・・・・・・ダイオード、Ｒｓ（２０Ω）
、Ｒｚ（４０ｒＤ・・・・・・抵抗、Ｒ８，Ｒ４・・・
・・・負荷抵抗、ＩＮ、ＩＮ・・・・・・入力端子、Ｏ
ＵＴ・・・・・・出力端子、ＶＤＤ（＋５Ｖ）・・・・
・・十電源、Ｖ、、（−５Ｖ）・・・・・・−電源。FIG. 1 is a circuit diagram of an embodiment of the present invention. CI... Capacitor, Q1~Q?・・・・・・
FET. Dl -D...Diode, Rs (20Ω)
, Rz (40rD...Resistance, R8, R4...
...Load resistance, IN, IN...Input terminal, O
UT...Output terminal, VDD (+5V)...
...10 power supplies, V, (-5V)...-power supplies.
Claims (1)
タと、この差動トランジスタの各出力をそれぞれ取出す
二組の出力回路と、この出力回路の一方をダミー出力と
しここから前記定電流源のトランジスタに一方の出力信
号を供給するフィードフォワード回路とを備え、前記出
力回路の他方から出力信号を取出すことを特徴とする一
出力差動増幅器。A pair of differential transistors each having a constant current source transistor, two sets of output circuits that take out each output of the differential transistors, and one of these output circuits is used as a dummy output from which one is connected to the constant current source transistor. and a feedforward circuit that supplies an output signal of the output circuit, and the output signal is extracted from the other of the output circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17459489A JPH0338904A (en) | 1989-07-05 | 1989-07-05 | One output differential amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17459489A JPH0338904A (en) | 1989-07-05 | 1989-07-05 | One output differential amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338904A true JPH0338904A (en) | 1991-02-20 |
Family
ID=15981301
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17459489A Pending JPH0338904A (en) | 1989-07-05 | 1989-07-05 | One output differential amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338904A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590849A (en) * | 1991-09-30 | 1993-04-09 | Nec Corp | Differential amplifier circuit |
-
1989
- 1989-07-05 JP JP17459489A patent/JPH0338904A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590849A (en) * | 1991-09-30 | 1993-04-09 | Nec Corp | Differential amplifier circuit |
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