JPH033890U - - Google Patents
Info
- Publication number
- JPH033890U JPH033890U JP6499389U JP6499389U JPH033890U JP H033890 U JPH033890 U JP H033890U JP 6499389 U JP6499389 U JP 6499389U JP 6499389 U JP6499389 U JP 6499389U JP H033890 U JPH033890 U JP H033890U
- Authority
- JP
- Japan
- Prior art keywords
- vertical synchronization
- signal
- synchronization signal
- timing
- pseudo vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000037431 insertion Effects 0.000 claims description 2
- 238000003780 insertion Methods 0.000 claims description 2
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の実施例に係る回路図、第２図
，，はそれぞれ同実施例の動作の説明に供
する各部の信号波形図、第３図ａ，ｂ，ｃそれぞ
れは再生映像信号と疑似垂直同期信号とその疑似
垂直同期信号が挿入された再生映像信号との波形
図であつて、従来の問題点の説明に供する図であ
る。
２……垂直同期信号分離回路、４……疑似垂直
同期信号挿入回路、６……ＯＲゲート、８……単
安定マルチバイブレータ（パルス出力手段）、Ｓ
１……再生映像信号、Ｓ２……第１の疑似垂直同
期信号、Ｓ３……垂直同期信号、Ｓ４……第２の
疑似垂直同期信号。
Fig. 1 is a circuit diagram according to an embodiment of the present invention, Figs. 2, 2, and 3 are signal waveform diagrams of various parts to explain the operation of the same embodiment, and Figs. 3 a, b, and c respectively show reproduced video signals. FIG. 2 is a waveform diagram of a pseudo vertical synchronization signal and a reproduced video signal into which the pseudo vertical synchronization signal is inserted, and is a diagram for explaining problems in the conventional art. 2... Vertical synchronizing signal separation circuit, 4... Pseudo vertical synchronizing signal insertion circuit, 6... OR gate, 8... Monostable multivibrator (pulse output means), S
1... Reproduction video signal, S2... First pseudo vertical synchronization signal, S3... Vertical synchronization signal, S4... Second pseudo vertical synchronization signal.
Claims (1)
るヘツド切換信号の発生タイミングに同期して生
成された第１の疑似垂直同期信号と、再生映像信
号から分離された垂直同期信号とが入力されるＯ
Ｒゲートと、 前記ＯＲゲートから出力される第１の疑似垂直
同期信号または垂直同期信号の内、先に出力され
てくる一方の信号でトリガされ、少なくともその
トリガタイミングから他方の信号の出力の終了タ
イミングまでの間にわたるパルス幅を有する信号
を第２の疑似垂直同期信号として出力するパルス
出力手段と、 を備えた疑似垂直同期信号の挿入タイミング制
御回路。[Claims for Utility Model Registration] A first pseudo vertical synchronization signal generated in synchronization with the generation timing of a head switching signal used for video head switching timing, and a vertical synchronization signal separated from a reproduced video signal. O to be input
It is triggered by one of the first pseudo vertical synchronization signal or vertical synchronization signal output from the R gate and the OR gate, and the output of the other signal ends at least from the trigger timing. A pseudo vertical synchronization signal insertion timing control circuit comprising: pulse output means for outputting a signal having a pulse width extending up to timing as a second pseudo vertical synchronization signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6499389U JPH033890U (en) | 1989-06-02 | 1989-06-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6499389U JPH033890U (en) | 1989-06-02 | 1989-06-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH033890U true JPH033890U (en) | 1991-01-16 |
Family
ID=31596423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6499389U Pending JPH033890U (en) | 1989-06-02 | 1989-06-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH033890U (en) |
-
1989
- 1989-06-02 JP JP6499389U patent/JPH033890U/ja active Pending
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