JPH0340510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a dynamic memory cell.

As this type of semiconductor memory device, one in which one memory cell is configured with one transistor is known. This has a configuration as shown in a plan view in FIG. 1, and an equivalent circuit as shown in FIG. 2. The outline of the structure will be explained for one cell. A semiconductor substrate, for example, a P-type Si substrate, is provided with n ⁺ regions 11, spaced apart from each other.
12 is provided, and a channel portion 13 is provided between the two regions.
is formed. A polycrystalline Si layer 14 is provided on the channel portion with an insulating film interposed therebetween. This polycrystalline Si layer 14 becomes a gate electrode. Another insulating film is provided on this polycrystalline Si layer 14 and connected to Al column lines 16 through predetermined openings 15. A MOS transistor composed of the n ⁺ regions 11, 12 and the gate electrode 14 is used for address selection.

On the other hand, a second layer is placed on the semiconductor substrate via an insulating film.
A polycrystalline Si layer 17 is provided, and a capacitive element 18 is formed between this Si layer 17 and the substrate.

Further, the n ⁺ region 11 is formed of a diffusion layer, for example, and serves as a digit line 19.

In such memory cells, for address selection
Since it is necessary to separate the gate electrode of the MOS transistor from the polycrystalline Si serving as one electrode of the capacitor, the cell area becomes large. Furthermore, the area occupied by the contact hole for making contact between the column line and the gate electrode was wasted. These results in a decrease in the degree of integration or an increase in the memory cell area, which is contrary to the recent trend towards higher integration of semiconductors.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor memory device with high integration density.

Another object of the present invention is to provide a semiconductor memory device having a large memory capacity compared to the area occupied by memory cells.

Still another object of the present invention is to provide a semiconductor memory device capable of high-speed reading.

Hereinafter, details of the present invention will be explained using the drawings. FIG. 3 is a plan view showing an embodiment of the apparatus of the present invention, and FIG. 4 is a sectional view taken along the line -- in FIG.

First, to explain the structure, for example, a relatively high resistance p ⁺ type silicon substrate 4 is used as a semiconductor substrate.
1 is prepared. A first electrode 43 is provided on a portion of this substrate with an insulating film, for example, silicon dioxide 42 interposed therebetween. As the insulating film, SiO ₂ ,
A laminate in which Si ₃ N ₄ , Al ₂ O ₃ , etc. are appropriately combined may also be used. This first electrode 43 was made of polycrystalline Si. Its production is carried out using normal CVD (Chemical
This was done using the Vapor Deposition method. Of course
It may be made of a metal material such as Mo, W, or Al. By applying a positive voltage to the first electrode 43 with respect to the semiconductor substrate 1, an n-type inversion layer 4 is formed on the surface of the substrate.
form 4. A capacitor 45 is constructed with this n-type inversion layer 44 and the first electrode 43 as both electrodes.

On the other hand, in the substrate apart from this n-type inversion layer 44,
An n ⁺ region 46 is provided. The n ⁺ region 46 is
For example, it is formed by a conventional diffusion method. this n ⁺
Region 46 extends in a direction perpendicular to the plane of the paper and is used as a digit line.

Of course, the n ⁺ region 46 may be manufactured by methods other than thermal diffusion, and may be formed from a conductive material.

A second electrode 48 is provided between the n ⁺ region 46 and the inversion layer 44 with a gate insulating film 47 interposed therebetween. For the gate insulating film 47, SiO ₂ with a thickness of 1000 Å was used, for example. Of course, other insulating materials may also be used. Further, although polycrystalline Si is used as the second electrode 48, metal materials such as Mo, W, and Al may also be used like the first electrode. This second electrode serves as a gate electrode, and the gate electrode 48, the n ⁺ region 46, the inversion layer 44, and the insulating film 47 constitute a MOS transistor 49.

Gate electrode 48 of this MOS transistor 49
extends over the first electrode 43 with an insulating film 50 interposed therebetween. This insulating film 50 is desirably thicker than the gate insulating film 47 if both insulating films are of the same quality. For example, the thickness is 8000 Å. Of course, the material of this insulating film 50 may include Al ₂ O ₃ , Si ₃ N ₄ or the like. The capacitance C ₂ of the portion sandwiched between the second electrode 48 extending on the insulating film 50 and the first electrode 43 is configured to be as small as possible compared to the gate-to-substrate capacitance C ₁ of the transistor 49. is desirable for high-speed operation.

For this purpose, the film thickness may be increased, or
The insulating film 50 may be made of a material with a low dielectric constant. A protective insulating film 51 is deposited on the gate electrode 48, and a predetermined opening 52 is provided in this film. Then, contact is made in this opening 52 with external wiring 53 forming a column line. The position where the aperture 52 is provided is particularly important in the present invention, and it is important that at least a part of the aperture is provided above the first electrode 43. FIG. 4 shows an example in which the entire opening is placed on the first electrode. In such an embodiment device, the area of the memory capacitor portion is reduced to 300 μm as in the conventional device.
m ² , the area occupied by the memory cell could be reduced to about 1/3 to 1/2 of the conventional device. As a result, the parasitic capacitance associated with the digit line was reduced, and even if the same sense amplifier was used as before, sensitivity and speed were improved.

The main points of the method for manufacturing the storage device shown in FIG. 4 will be explained. After providing the first electrode 43 on the insulating film 42, a thick insulating film 50 is deposited by, for example, CVD method. Then, at least the top of the first electrode 43 is left,
Expose the surface of the substrate at the gate of the MOS transistor. Then, in this state, a gate oxide film 47 is formed by thermal oxidation. MOS of the first electrode 43
The portion adjacent to the transistor is thin because it is oxidized with some of the thick insulating film 50 removed due to photographic exposure.

Now, memory cells having such a configuration are used in a matrix arrangement as shown in FIG. 5, for example. In the figure, 101, 102, etc. indicate individual memory cells, and 103, etc. indicate a sense amplifier. The memory cell in row i and column j will now be explained in conjunction with FIG. A case will be described in which information is written to the memory cell in the i-th row and the j-th column. To the board 41-
5 Volt and +12 Volt are applied to the first electrode 43. As a result, free electrons are induced on the surface of the substrate 41 and an inversion layer 44 is formed. When +12 Volt is applied to the address selection line or column line 53 in this state, the potential of the gate electrode 48 of the transistor 49 becomes +12 Volt, and the transistor is turned on. As a result, data from the daisy line 46 is written into the memory element 45.

Next, when the column line 53 is set to 0 Volt and the transistor is turned off, the data is transferred to the capacitive element 45.
is accumulated in

When such memory cells are arranged in a matrix to form a large capacity memory, the digit line 46 has a large capacity compared to the memory capacity 45 of the cell. Therefore, when reading memory information, if a voltage is applied to the gate electrode 48 of the transistor 49 to open the gate, the charge in the memory cell is masked by the capacitance of the digit line, making it difficult to sense with a sense amplifier. Therefore, it is desirable that the capacitance of the memory cell be larger than the capacitance of the digit line. Conversely, if the capacitance of the memory cells is the same, sensitivity and speed can be improved if the parasitic capacitance associated with the digit line can be reduced. This result is as described above.

Furthermore, a gate extension part of the MOS transistor,
Since the capacitance with the first electrode 43 is small, the sixth
As shown in the equivalent circuit in the figure, the parasitic capacitance of the memory cell
Cpij also becomes small. Therefore, it is possible to use the column line j even if its driving capacity is small. Furthermore, even if the column line is made of Al or the like, it generally has distributed resistance, and a delay in the CR time constant occurs due to the capacitance of the memory cell. Since this C becomes small, it becomes possible to read and write at high speed. In particular, it is effective in realizing large-capacity memory systems.

In the above embodiments, the case where the inversion region 44 is formed has been described, but the n ⁺
If the region is formed, there is no need to particularly apply an inversion voltage to the first electrode. Furthermore, it goes without saying that the present invention is applicable to not only n-channel devices but also p-channel devices.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a conventional one-transistor/one-cell memory device, FIG. 2 is an equivalent circuit diagram of the device shown in FIG. 1, and FIG. 3 explains an embodiment of the device of the present invention. 4 is a sectional view taken along the line -- in FIG. 3, FIG. 5 is a diagram for explaining a memory matrix arrangement, and FIG. 6 is an equivalent circuit diagram for explaining the effects of the present invention. In the figure, 11, 12...n ⁺ area, 13...
... Channel part, 14, 17 ... Polycrystalline Si, 15
...Opening portion, 16...Column line, 18...Capacitive element, 41...p ^- Si, 42... _SiO2 , 43...First electrode, 44...Inversion layer, 45...Capacitor,
46...n ⁺ region, 47...gate insulating film, 48
...Second electrode, 49...MOS transistor, 5
0... Insulating film, 51... Protective insulating film, 52... Opening portion, 53... Wiring, 101, 102... Memory cell, 103... Sense amplifier.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a capacitor electrode formed on a first region of the surface of the semiconductor substrate via a first insulating film and facing the first region, and spaced apart from the first region. a second region formed on the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and forming a digit line; and a second region existing on the surface of the semiconductor substrate between the first and second regions via a second insulating film. a gate electrode having a first portion extending from the first portion and provided on the capacitor electrode with a third insulating film interposed therebetween; a fourth insulating film that covers the gate electrode and has an opening over the second portion of the gate electrode; and a second portion of the gate electrode that is present on the fourth insulating film;
A semiconductor memory device comprising an external wiring that is contacted through the opening and serves as a column line, and wherein the thickness of the third insulating film is greater than the thickness of the capacitor electrode.