JPH0341316U - - Google Patents
Info
- Publication number
- JPH0341316U JPH0341316U JP10197689U JP10197689U JPH0341316U JP H0341316 U JPH0341316 U JP H0341316U JP 10197689 U JP10197689 U JP 10197689U JP 10197689 U JP10197689 U JP 10197689U JP H0341316 U JPH0341316 U JP H0341316U
- Authority
- JP
- Japan
- Prior art keywords
- output
- transistor
- current
- voltage
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
従来の一例の回路図、第３図は第２図に示す回路
の動作を説明するための特性図である。
１……入力端子、２……出力端子、３……差動
アンプ、４……ツエナーダイオード、Ｑ１……出
力トランジスタ、Ｑ２……制御トランジスタ、Ｑ
３，Ｑ４……カレントミラー回路のトランジスタ
、ＲＢ……抵抗。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIG. 3 is a characteristic diagram for explaining the operation of the circuit shown in FIG. 1...Input terminal, 2...Output terminal, 3...Differential amplifier, 4...Zener diode, Q1...Output transistor, Q2 ... Control transistor, Q
3 , Q 4 ...Transistor of current mirror circuit, RB...Resistor.
Claims (1)
動アンプの出力にて出力トランジスタのベースに
接続された制御トランジスタを介して読出力トラ
ンジスタを制御して定電圧を得る一方、電源投入
後の出力電圧が非安定領域にある期間、カレント
ミラー回路で構成された２つのトランジスタのう
ち上記出力トランジスタの出力端子と上記差動ア
ンプの出力端子との間に接続された電流出力側ト
ランジスタに流れる電流にて上記出力トランジス
タのベース電流を少なくして入力電流の急上昇を
抑制する構成の直流定電圧回路において、 前記カレントミラー回路を構成する２つのトラ
ンジスタのうちの電流入力側トランジスタを、前
記出力トランジスタの出力端子と、抵抗を介して
前記出力トランジスタのベースとの間に接続し、 前記電源投入による、前記出力トランジスタの
出力端子と、前記電流入力側トランジスタと前記
抵抗との接続点との間の電圧の増大にて前記電流
入力側トランジスタを導通させ、この導通電流に
て前記出力トランジスタのベース電流を減少させ
る構成としてなる直流定電圧回路。[Claims for Utility Model Registration] At the output of the differential amplifier that compares the divided output voltage and the reference voltage, the readout transistor is controlled via a control transistor connected to the base of the output transistor to maintain a constant voltage. On the other hand, during the period when the output voltage is in the unstable region after the power is turned on, the voltage that is connected between the output terminal of the output transistor and the output terminal of the differential amplifier of the two transistors configured in the current mirror circuit is In a DC constant voltage circuit configured to suppress a sudden increase in input current by reducing the base current of the output transistor with the current flowing through the current output side transistor, the current input of the two transistors forming the current mirror circuit A side transistor is connected between an output terminal of the output transistor and a base of the output transistor via a resistor, and when the power is turned on, the output terminal of the output transistor, the current input side transistor, and the resistor are connected. A direct current constant voltage circuit configured to cause the current input side transistor to conduct by increasing the voltage between it and a connection point thereof, and to reduce the base current of the output transistor by this conduction current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10197689U JPH0341316U (en) | 1989-08-31 | 1989-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10197689U JPH0341316U (en) | 1989-08-31 | 1989-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0341316U true JPH0341316U (en) | 1991-04-19 |
Family
ID=31650898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10197689U Pending JPH0341316U (en) | 1989-08-31 | 1989-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0341316U (en) |
-
1989
- 1989-08-31 JP JP10197689U patent/JPH0341316U/ja active Pending